[llvm] r192895 - [mips][msa] Added lsa instruction
Daniel Sanders
daniel.sanders at imgtec.com
Thu Oct 17 06:38:21 PDT 2013
Author: dsanders
Date: Thu Oct 17 08:38:20 2013
New Revision: 192895
URL: http://llvm.org/viewvc/llvm-project?rev=192895&view=rev
Log:
[mips][msa] Added lsa instruction
Added:
llvm/trunk/test/CodeGen/Mips/msa/special.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsMips.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
Modified: llvm/trunk/include/llvm/IR/IntrinsicsMips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsMips.td?rev=192895&r1=192894&r2=192895&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsMips.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsMips.td Thu Oct 17 08:38:20 2013
@@ -1251,6 +1251,12 @@ def int_mips_ldi_w : GCCBuiltin<"__built
def int_mips_ldi_d : GCCBuiltin<"__builtin_msa_ldi_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_i32_ty], [IntrNoMem]>;
+// This instruction is part of the MSA spec but it does not share the
+// __builtin_msa prefix because it operates on the GPR registers.
+def int_mips_lsa : GCCBuiltin<"__builtin_mips_lsa">,
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem]>;
+
def int_mips_madd_q_h : GCCBuiltin<"__builtin_msa_madd_q_h">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem]>;
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=192895&r1=192894&r2=192895&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Thu Oct 17 08:38:20 2013
@@ -314,3 +314,9 @@ class MSA_VECS10_FMT<bits<5> major, bits
let Inst{25-21} = major;
let Inst{5-0} = minor;
}
+
+class SPECIAL_LSA_FMT: MSAInst {
+ let Inst{25-21} = 0b000000;
+ let Inst{10-8} = 0b000;
+ let Inst{5-0} = 0b000101;
+}
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=192895&r1=192894&r2=192895&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Thu Oct 17 08:38:20 2013
@@ -61,6 +61,10 @@ def MipsVExtractZExt : SDNode<"MipsISD::
// Operands
+def uimm2 : Operand<i32> {
+ let PrintMethod = "printUnsignedImm";
+}
+
def uimm3 : Operand<i32> {
let PrintMethod = "printUnsignedImm";
}
@@ -109,6 +113,8 @@ def vsplat_simm5 : Operand<vAny>;
def vsplat_simm10 : Operand<vAny>;
+def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
+
// Pattern fragments
def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i8)>;
@@ -762,6 +768,8 @@ class LDI_H_ENC : MSA_I10_FMT<0b010, 0b
class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>;
class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>;
+class LSA_ENC : SPECIAL_LSA_FMT;
+
class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
@@ -2038,6 +2046,14 @@ class LDI_H_DESC : MSA_I10_LDI_DESC_BASE
class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128W>;
class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128D>;
+class LSA_DESC {
+ dag OutOperandList = (outs GPR32:$rd);
+ dag InOperandList = (ins GPR32:$rs, GPR32:$rt, uimm2:$sa);
+ string AsmString = "lsa\t$rd, $rs, $rt, $sa";
+ list<dag> Pattern = [(set GPR32:$rd, (add GPR32:$rs, (shl GPR32:$rt,
+ immZExt2Lsa:$sa)))];
+ InstrItinClass Itinerary = NoItinerary;
+}
class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
MSA128HOpnd>;
@@ -2893,6 +2909,8 @@ def LDI_H : LDI_H_ENC, LDI_H_DESC;
def LDI_W : LDI_W_ENC, LDI_W_DESC;
def LDI_D : LDI_D_ENC, LDI_D_DESC;
+def LSA : LSA_ENC, LSA_DESC;
+
def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=192895&r1=192894&r2=192895&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Thu Oct 17 08:38:20 2013
@@ -1403,6 +1403,12 @@ SDValue MipsSETargetLowering::lowerINTRI
case Intrinsic::mips_ldi_w:
case Intrinsic::mips_ldi_d:
return lowerMSASplatImm(Op, 1, DAG);
+ case Intrinsic::mips_lsa: {
+ EVT ResTy = Op->getValueType(0);
+ return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
+ DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
+ Op->getOperand(2), Op->getOperand(3)));
+ }
case Intrinsic::mips_maddv_b:
case Intrinsic::mips_maddv_h:
case Intrinsic::mips_maddv_w:
Added: llvm/trunk/test/CodeGen/Mips/msa/special.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/special.ll?rev=192895&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/special.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/msa/special.ll Thu Oct 17 08:38:20 2013
@@ -0,0 +1,26 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
+
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
+
+define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+ %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
+ ret i32 %0
+}
+
+declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
+
+; CHECK: llvm_mips_lsa_test:
+; CHECK: lsa {{\$[0-9]+}}, {{\$[0-9]+}}, {{\$[0-9]+}}, 2
+; CHECK: .size llvm_mips_lsa_test
+
+define i32 @lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+ %0 = shl i32 %b, 2
+ %1 = add i32 %a, %0
+ ret i32 %1
+}
+
+; CHECK: lsa_test:
+; CHECK: lsa {{\$[0-9]+}}, {{\$[0-9]+}}, {{\$[0-9]+}}, 2
+; CHECK: .size lsa_test
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