[llvm] r192790 - [SystemZ] Handle extensions in RxSBG optimizations

[Richard Sandiford]

Author: rsandifo
Date: Wed Oct 16 08:35:13 2013
New Revision: 192790

URL: http://llvm.org/viewvc/llvm-project?rev=192790&view=rev
Log:
[SystemZ] Handle extensions in RxSBG optimizations

The input to an RxSBG operation can be narrower as long as the upper bits
are don't care.  This fixes a FIXME added in r192783.

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/SystemZ/shift-10.ll

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=192790&r1=192789&r2=192790&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Wed Oct 16 08:35:13 2013
@@ -107,7 +107,8 @@ static uint64_t allOnes(unsigned int Cou
 //
 //   (and (rotl Input, Rotate), Mask)
 //
-// otherwise.  The value has BitSize bits.
+// otherwise.  The output value has BitSize bits, although Input may be
+// narrower (in which case the upper bits are don't care).
 struct RxSBGOperands {
   RxSBGOperands(unsigned Op, SDValue N)
     : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
@@ -762,7 +763,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
 
   case ISD::ROTL: {
     // Any 64-bit rotate left can be merged into the RxSBG.
-    if (RxSBG.BitSize != 64)
+    if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
       return false;
     ConstantSDNode *CountNode
       = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
@@ -774,6 +775,19 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
     return true;
   }
       
+  case ISD::SIGN_EXTEND:
+  case ISD::ZERO_EXTEND:
+  case ISD::ANY_EXTEND: {
+    // Check that the extension bits are don't-care (i.e. are masked out
+    // by the final mask).
+    unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
+    if (shiftedInBitsMatter(RxSBG, RxSBG.BitSize - InnerBitSize, false))
+      return false;
+
+    RxSBG.Input = N.getOperand(0);
+    return true;
+  }
+
   case ISD::SHL: {
     ConstantSDNode *CountNode =
       dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
@@ -781,7 +795,8 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
       return false;
 
     uint64_t Count = CountNode->getZExtValue();
-    if (Count < 1 || Count >= RxSBG.BitSize)
+    unsigned BitSize = N.getValueType().getSizeInBits();
+    if (Count < 1 || Count >= BitSize)
       return false;
 
     if (RxSBG.Opcode == SystemZ::RNSBG) {
@@ -791,7 +806,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
         return false;
     } else {
       // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
-      if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count) << Count))
+      if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count) << Count))
         return false;
     }
 
@@ -808,7 +823,8 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
       return false;
 
     uint64_t Count = CountNode->getZExtValue();
-    if (Count < 1 || Count >= RxSBG.BitSize)
+    unsigned BitSize = N.getValueType().getSizeInBits();
+    if (Count < 1 || Count >= BitSize)
       return false;
 
     if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
@@ -819,7 +835,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(Rx
     } else {
       // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
       // which is similar to SLL above.
-      if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count)))
+      if (!refineRxSBGMask(RxSBG, allOnes(BitSize - Count)))
         return false;
     }
 
@@ -852,7 +868,8 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZer
   RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
   unsigned Count = 0;
   while (expandRxSBG(RISBG))
-    Count += 1;
+    if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND)
+      Count += 1;
   if (Count == 0)
     return 0;
   if (Count == 1) {
@@ -909,7 +926,8 @@ SDNode *SystemZDAGToDAGISel::tryRxSBG(SD
   unsigned Count[] = { 0, 0 };
   for (unsigned I = 0; I < 2; ++I)
     while (expandRxSBG(RxSBG[I]))
-      Count[I] += 1;
+      if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND)
+        Count[I] += 1;
 
   // Do nothing if neither operand is suitable.
   if (Count[0] == 0 && Count[1] == 0)

Modified: llvm/trunk/test/CodeGen/SystemZ/shift-10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/shift-10.ll?rev=192790&r1=192789&r2=192790&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/shift-10.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/shift-10.ll Wed Oct 16 08:35:13 2013
@@ -52,11 +52,10 @@ define i64 @f4(i32 %a) {
 }
 
 ; Repeat the previous test in a case where all bits outside the
-; bottom 3 matter.  FIXME: can still use RISBG here.
+; bottom 3 matter.
 define i64 @f5(i32 %a) {
 ; CHECK-LABEL: f5:
-; CHECK: srl %r2, 30
-; CHECK: sllg %r2, %r2, 33
+; CHECK: risbg %r2, %r2, 29, 158, 3
 ; CHECK: lhi %r2, 7
 ; CHECK: br %r14
   %shr = lshr i32 %a, 30