[llvm] r192565 - Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.

[Craig Topper]

Author: ctopper
Date: Sun Oct 13 20:21:22 2013
New Revision: 192565

URL: http://llvm.org/viewvc/llvm-project?rev=192565&view=rev
Log:
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=192565&r1=192564&r2=192565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Oct 13 20:21:22 2013
@@ -2710,6 +2710,7 @@ multiclass sse12_extr_sign_mask<Register
                 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
                      [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
              Sched<[WriteVecLogic]>;
+  let isAsmParserOnly = 1, hasSideEffects = 0 in
   def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
                 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
                 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
@@ -4284,14 +4285,21 @@ def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
 // Insert
 let Predicates = [HasAVX] in {
   defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
+  let isAsmParserOnly = 1, hasSideEffects = 0 in
   def  VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
        (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
        "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
        []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
 }
 
-let Constraints = "$src1 = $dst" in
-  defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
+let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in {
+  defm PINSRW : sse2_pinsrw, TB, OpSize;
+  let isAsmParserOnly = 1, hasSideEffects = 0 in
+  def  PINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
+       (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
+       "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+       []>, TB, OpSize, Sched<[WriteShuffle]>;
+} // Predicates = [UseSSE2], Constraints = "$src1 = $dst"
 
 } // ExeDomain = SSEPackedInt
 

Modified: llvm/trunk/test/MC/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-encoding.s?rev=192565&r1=192564&r2=192565&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-encoding.s Sun Oct 13 20:21:22 2013
@@ -235,3 +235,11 @@ sha256msg2 (%rax), %xmm2
 // CHECK: pmovmskb	%xmm5, %rcx
 // CHECK:  encoding: [0x66,0x0f,0xd7,0xcd]
         	pmovmskb	%xmm5,%rcx
+
+// CHECK: pinsrw $3, %ecx, %xmm5
+// CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]
+          pinsrw $3, %ecx, %xmm5
+
+// CHECK: pinsrw $3, %rcx, %xmm5
+// CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]
+          pinsrw $3, %rcx, %xmm5