[PATCH] ARM: correct liveness on ldm/stm combiner

[Renato Golin]

Hi Tim,

Patch looks good. Did you check with Matthias about sub-register liveness
analysis? His patch might change yours...

A few comments below...


On 9 October 2013 16:05, Tim Northover <t.p.northover at gmail.com> wrote:

> When we had a sequence like:
>
>         s1 = VLDRS [r0, 1], Q0<imp-def>
>         s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
>         s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
>         s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
>
> we were gathering the {s0, s1} loads below the s3 load. This is fine, but
> confused the verifier since now the s3 load had Q0<imp-use> with no
> definition above it.
>

You mean the order becomes: s3, s1, s0, s2? or s1, s0, s3, s2? The former
will look broken, the latter, not so much.


@@ -432,6 +509,7 @@
>
       memOps[i].isKill = true;
>      }
>      MBB.erase(memOps[i].MBBI);
> +
>

Unnecessary space change.


+define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) {
> +; CHECK-LABEL: foo:
> +; CHECK: vldr s3, [r0, #8]
> +; CHECK: vldmia r0, {s0, s1}
> +; CHECK: vldr s2, [r0, #16]
>

Will it always be in this order? I thought the requirement was to make sure
it does call a vldmia on {s0, s1} instead of 2 separate loads. In that
case, a CHECK-DAG would be safer, no?

cheers,
--renato
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