[PATCH] R600: Fix trunc i64 to i32 on SI
Matt Arsenault
Matthew.Arsenault at amd.com
Wed Oct 9 16:20:22 PDT 2013
http://llvm-reviews.chandlerc.com/D1882
Files:
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
test/CodeGen/R600/unaligned-load-store.ll
Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -311,6 +311,8 @@
SDValue Val = ST->getValue();
EVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
+ unsigned AS = ST->getAddressSpace();
+
SDLoc dl(ST);
if (ST->getMemoryVT().isFloatingPoint() ||
ST->getMemoryVT().isVector()) {
@@ -343,7 +345,7 @@
SDValue Store = DAG.getTruncStore(Chain, dl,
Val, StackPtr, MachinePointerInfo(),
StoredVT, false, false, 0);
- SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
+ SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
SmallVector<SDValue, 8> Stores;
unsigned Offset = 0;
@@ -408,8 +410,9 @@
Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
ST->getPointerInfo(), NewStoredVT,
ST->isVolatile(), ST->isNonTemporal(), Alignment);
+
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
- DAG.getConstant(IncrementSize, TLI.getPointerTy()));
+ DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
Alignment = MinAlign(Alignment, IncrementSize);
Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
Index: test/CodeGen/R600/unaligned-load-store.ll
===================================================================
--- /dev/null
+++ test/CodeGen/R600/unaligned-load-store.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
+
+define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
+; CHECK-LABEL: @unaligned_load_store_i32:
+; CHECK: V_ADD_I32_e64 [[REG:VGPR[0-9]+]]
+; DS_READ_U8 {{VGPR[0-9]+}}, 0, [[REG]]
+entry:
+ %v = load i32 addrspace(3)* %p, align 1
+ store i32 %v, i32 addrspace(3)* %r, align 1
+ ret void
+}
+
+define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
+; CHECK-LABEL: @unaligned_load_store_v4i32:
+; CHECK: V_ADD_I32_e64 [[REG:VGPR[0-9]+]]
+; DS_READ_U8 {{VGPR[0-9]+}}, 0, [[REG]]
+entry:
+ %v = load <4 x i32> addrspace(3)* %p, align 1
+ store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1
+ ret void
+}
+
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