[PATCH] [PATCH][AArch64] implement aarch64 neon vector load/store N-element structure class AdvSIMD (lselem)

[Hao]

Hi t.p.northover,

Use 6 super registers: DPair/QPair/DTriple/QTriple/DQuad/QQuad to represent 2/3/4 consecutive registers.

http://llvm-reviews.chandlerc.com/D1869

Files:
  include/llvm/CodeGen/ValueTypes.h
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrNEON.td
  lib/Target/AArch64/AArch64RegisterInfo.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
  lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
  lib/Target/AArch64/Utils/AArch64BaseInfo.h
  test/MC/AArch64/neon-diagnostics.s
  tools/clang/include/clang/Basic/arm_neon.td
  tools/clang/lib/CodeGen/CGBuiltin.cpp
  tools/clang/test/CodeGen/aarch64-neon-intrinsics.c
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D1869.1.patch
Type: text/x-patch
Size: 99764 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20131009/8e8828c4/attachment.bin>