[llvm] r192130 - Add Mips16 patterns for sign extend byte and sign extend halfword.

[Reed Kotler]

Author: rkotler
Date: Mon Oct  7 15:46:19 2013
New Revision: 192130

URL: http://llvm.org/viewvc/llvm-project?rev=192130&view=rev
Log:
Add Mips16 patterns for sign extend byte and sign extend halfword.


Modified:
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=192130&r1=192129&r2=192130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Mon Oct  7 15:46:19 2013
@@ -343,6 +343,14 @@ class FRR16_JALRC_ins<bits<1> nd, bits<1
   FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
               !strconcat(asmstr, "\t $rx"), [], itin> ;
 
+class FRR_SF16_ins
+  <bits<5> _funct, bits<3> _subfunc,
+    string asmstr, InstrItinClass itin>:
+  FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
+           !strconcat(asmstr, "\t $rx"),
+           [], itin> {
+  let Constraints = "$rx_ = $rx";
+  }
 //
 // RRR-type instruction format
 //
@@ -952,6 +960,22 @@ def SbRxRyOffMemX16:
   FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
 
 //
+// Format: SEB rx MIPS16e
+// Purpose: Sign-Extend Byte
+// Sign-extend least significant byte in register rx.
+//
+def SebRx16
+  : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
+
+//
+// Format: SEH rx MIPS16e
+// Purpose: Sign-Extend Halfword
+// Sign-extend least significant word in register rx.
+//
+def SehRx16
+  : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
+
+//
 // The Sel(T) instructions are pseudos
 // T means that they use T8 implicitly.
 //
@@ -1815,6 +1839,12 @@ def : Mips16Pat<(i32 (extloadi16  addr16
 
 def: Mips16Pat<(trap), (Break16)>;
 
+def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
+                (SebRx16 CPU16Regs:$val)>;
+
+def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
+                (SehRx16 CPU16Regs:$val)>;
+
 def GotPrologue16:   
   MipsPseudo16<
     (outs CPU16Regs:$rh, CPU16Regs:$rl),

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll?rev=192130&r1=192129&r2=192130&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll Mon Oct  7 15:46:19 2013
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s 
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s 
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 -soft-float -mips16-hard-float   < %s | FileCheck %s 
 
 define signext i8 @A(i8 %e.0, i8 signext %sum)  nounwind {
 entry: