[llvm] r192037 - Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).

[Craig Topper]

Author: ctopper
Date: Sat Oct  5 12:17:53 2013
New Revision: 192037

URL: http://llvm.org/viewvc/llvm-project?rev=192037&view=rev
Log:
Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/CodeGen/X86/tbm_patterns.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=192037&r1=192036&r2=192037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sat Oct  5 12:17:53 2013
@@ -2014,6 +2014,12 @@ let Predicates = [HasTBM] in {
   def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
             (BLCI_64rr GR64:$src)>;
 
+  // Extra patterns because opt can optimize the above patterns to this.
+  def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
+            (BLCI_32rr GR32:$src)>;
+  def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
+            (BLCI_64rr GR64:$src)>;
+
   def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
             (BLCIC_32rr GR32:$src)>;
   def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),

Modified: llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=192037&r1=192036&r2=192037&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm_patterns.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm_patterns.ll Sat Oct  5 12:17:53 2013
@@ -84,6 +84,26 @@ entry:
   ret i64 %2
 }
 
+define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind readnone {
+entry:
+  ; CHECK-LABEL: test_x86_tbm_blci_u32_b:
+  ; CHECK-NOT: mov
+  ; CHECK: blci %
+  %0 = sub i32 -2, %a
+  %1 = or i32 %0, %a
+  ret i32 %1
+}
+
+define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind readnone {
+entry:
+  ; CHECK-LABEL: test_x86_tbm_blci_u64_b:
+  ; CHECK-NOT: mov
+  ; CHECK: blci %
+  %0 = sub i64 -2, %a
+  %1 = or i64 %0, %a
+  ret i64 %1
+}
+
 define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
 entry:
   ; CHECK-LABEL: test_x86_tbm_blcic_u32: