[PATCH][AArch64] implement aarch64 neon load/store instructions class AdvSIMD (lselem)

[Tim Northover]

Hi Hao,

> The second argument of DTriple should be "v3i64". As there is no v3i64, I
> have to use untyped. But then I can't get the DTripleRegClass in
> getRegClassFor(MVT VT) of AArch64ISelLowering.cpp.

Why do you think you need this? Can't you just create an untyped
REG_SEQUENCE for them? The node already seems to encode the
RegisterClass directly. I'd expect something like this to work:

SDNode *AArch64DAGToDAGISel::createDRegTripleNode(SDValue V0, SDValue
V1, SDValue V2) {
  SDLoc dl(V0.getNode());
  SDValue RegClass =
      CurDAG->getTargetConstant(AArch64::DTripleRegClassID, MVT::i32);
  SDValue SubReg0 = CurDAG->getTargetConstant(AArch64::qsub_0, MVT::i32);
  SDValue SubReg1 = CurDAG->getTargetConstant(AArch64::qsub_1, MVT::i32);
  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::untyped,
                                Ops);
}

Hopefully it will use the hint you give it there rather than asking
for a registerclass from getRegClassFor. I'm sure we can get it
working somehow without adding v3i64 (or v3v8i8 or whatever), send me
a patch if you get stuck and I'll see what I can do with it.

Cheers.

Tim.