[llvm] r191905 - Added checking code whehter target supports specific dag combining about rotate
Jin-Gu Kang
jaykang10 at imrc.kist.re.kr
Thu Oct 3 08:58:48 PDT 2013
Author: jaykang10
Date: Thu Oct 3 10:58:48 2013
New Revision: 191905
URL: http://llvm.org/viewvc/llvm-project?rev=191905&view=rev
Log:
Added checking code whehter target supports specific dag combining about rotate
or not. The corresponding dag patterns are as following:
"DAGCombier::MatchRotate" function in DAGCombiner.cpp
Pattern1
// fold (or (shl (*ext x), (*ext y)),
// (srl (*ext x), (*ext (sub 32, y)))) ->
// (*ext (rotl x, y))
// fold (or (shl (*ext x), (*ext y)),
// (srl (*ext x), (*ext (sub 32, y)))) ->
// (*ext (rotr x, (sub 32, y)))
pattern2
// fold (or (shl (*ext x), (*ext (sub 32, y))),
// (srl (*ext x), (*ext y))) ->
// (*ext (rotl x, y))
// fold (or (shl (*ext x), (*ext (sub 32, y))),
// (srl (*ext x), (*ext y))) ->
// (*ext (rotr x, (sub 32, y)))
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=191905&r1=191904&r2=191905&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Oct 3 10:58:48 2013
@@ -3415,12 +3415,16 @@ SDNode *DAGCombiner::MatchRotate(SDValue
// (*ext (rotr x, (sub 32, y)))
SDValue LArgExtOp0 = LHSShiftArg.getOperand(0);
EVT LArgVT = LArgExtOp0.getValueType();
- if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
- SDValue V =
- DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
- LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
- return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
- }
+ bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT);
+ bool HasROTLWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTL, LArgVT);
+ if (HasROTRWithLArg || HasROTLWithLArg) {
+ if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
+ SDValue V =
+ DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
+ LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
+ return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
+ }
+ }
}
}
} else if (LExtOp0.getOpcode() == ISD::SUB &&
@@ -3444,11 +3448,15 @@ SDNode *DAGCombiner::MatchRotate(SDValue
// (*ext (rotr x, (sub 32, y)))
SDValue RArgExtOp0 = RHSShiftArg.getOperand(0);
EVT RArgVT = RArgExtOp0.getValueType();
- if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
- SDValue V =
- DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, RArgVT,
- RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt);
- return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode();
+ bool HasROTRWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTR, RArgVT);
+ bool HasROTLWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTL, RArgVT);
+ if (HasROTRWithRArg || HasROTLWithRArg) {
+ if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
+ SDValue V =
+ DAG.getNode(HasROTRWithRArg ? ISD::ROTR : ISD::ROTL, DL, RArgVT,
+ RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt);
+ return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode();
+ }
}
}
}
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