[llvm] r191859 - [llvm-c][Disassembler] Add an option to print latency information in
Quentin Colombet
qcolombet at apple.com
Thu Oct 3 10:56:05 PDT 2013
Hi Hal,
On Oct 2, 2013, at 6:16 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
>>
>>
>>
>>
>> On Oct 2, 2013, at 5:08 PM, Quentin Colombet < qcolombet at apple.com >
>> wrote:
>>
>>
>>
>>
>>
>> -Quentin
>>
>>
>> On Oct 2, 2013, at 4:09 PM, Hal Finkel < hfinkel at anl.gov > wrote:
>>
>>
>>
>> ----- Original Message -----
>>
>>
>> Hi Hal,
>>
>> On Oct 2, 2013, at 3:21 PM, Hal Finkel < hfinkel at anl.gov > wrote:
>>
>>
>>
>> Quentin,
>>
>> This looks interesting. Does it work with itineraries? (and if not,
>> could we make it work with them?)
>> No, it does not work with itineraries.
>>
>> From my understanding, the representation using itineraries is the
>> old way of modeling the scheduling information so I did not bother
>> looking into it.
>> Am I wrong?
>>
>> It is the old way, but until we have post-RA MI scheduling, we can't
>> entirely switch (at least I can't, and I don't know if there are
>> other issues that will prevent others from switching).
>> I had a look and it should be doable if we keep a reference on the
>> CPU.
>> I will see if I can come up with something.
>> That patch should to the trick, also I was not able to produce an
>> instruction that does not return -1 from the itinerary info with the
>> atom cpu.
>> Apparently, I am always failing into this case from
>> InstrItineraryData::getOperandLatency with both FirstIdx and LastIdx
>> equal to 0.
>> 00186 if ((FirstIdx + OperandIdx) >= LastIdx) 00187 return -1;
>>
>>
>> Do you have an object file I can use for testing?
>
> Sorry, my fault. I thought that they had changed (fixed) this, but it seems that they've not yet. The Atom itinerary does not define any latencies, so this won't work as a test. How about using one of the ARM targets with itineraries? (both ARMScheduleA9 and ARMScheduleA8 seem to define latencies).
>
I tested the proposed patch for the itineraries with cortex-a8 and it works great.
Here is an example:
bic r4, r4, #0xf @ Latency: 2
mov sp, r4
vst1.64 {d8, d9}, [r4:128]
vmov d9, r2, r3 @ Latency: 2
I have committed the patch in r191916.
Cheers,
-Quentin
> -Hal
>
>>
>> Thanks.
>>
>>
>> -Quentin
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> -Quentin
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> What would be really quite useful is if we had the scheduler tag
>> the MIs with their expected dispatch latency (meaning number of
>> stall cycles for an in-order core), and printed that in the
>> assembly output.
>> Agreed, but it requires far more infrastructural work, because the
>> scheduling API is available at MI level.
>>
>> This feature was intended to give a rough idea of that is expensive
>> and what is not.
>>
>> Makes perfect sense to me. I just figured that I mention my desire so
>> that we can think about how to accomplish it at some point.
>>
>> Thanks again,
>> Hal
>>
>>
>>
>>
>> Quentin
>>
>>
>>
>> -Hal
>>
>> ----- Original Message -----
>>
>>
>> Author: qcolombet
>> Date: Wed Oct 2 17:07:57 2013
>> New Revision: 191859
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=191859&view=rev
>> Log:
>> [llvm-c][Disassembler] Add an option to print latency information
>> in
>> disassembled output alongside the instructions.
>> E.g., on a vector shuffle operation with a memory operand,
>> disassembled
>> outputs are:
>> * Without the option:
>> vpshufd $-0x79, (%rsp), %xmm0
>>
>> * With the option:
>> vpshufd $-0x79, (%rsp), %xmm0 ## Latency: 5
>>
>> The printed latency is extracted from the schedule model available
>> in
>> the
>> disassembler context. Thus, this option has no effect if there is
>> not
>> a
>> scheduling model for the target.
>> This boils down to one may need to specify the CPU string, so that
>> this
>> option could have an effect.
>>
>> Note: Latency < 2 are not printed.
>>
>> This part of < rdar://problem/14687488 >.
>>
>> Modified:
>> llvm/trunk/include/llvm-c/Disassembler.h
>> llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
>> llvm/trunk/lib/MC/MCDisassembler/Disassembler.h
>>
>> Modified: llvm/trunk/include/llvm-c/Disassembler.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Disassembler.h?rev=191859&r1=191858&r2=191859&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm-c/Disassembler.h (original)
>> +++ llvm/trunk/include/llvm-c/Disassembler.h Wed Oct 2 17:07:57
>> 2013
>> @@ -172,6 +172,8 @@ int LLVMSetDisasmOptions(LLVMDisasmConte
>> #define LLVMDisassembler_Option_AsmPrinterVariant 4
>> /* The option to set comment on instructions */
>> #define LLVMDisassembler_Option_SetInstrComments 8
>> + /* The option to print latency information alongside
>> instructions
>> */
>> +#define LLVMDisassembler_Option_PrintLatency 16
>>
>> /**
>> * Dispose of a disassembler context.
>>
>> Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=191859&r1=191858&r2=191859&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
>> +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Oct 2
>> 17:07:57 2013
>> @@ -174,6 +174,52 @@ static void emitComments(LLVMDisasmConte
>> DC->CommentStream.resync();
>> }
>>
>> +/// \brief Gets latency information for \p Inst, based on \p DC
>> information.
>> +/// \return The maximum expected latency over all the definitions
>> or
>> -1
>> +/// if no information are available.
>> +static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
>> {
>> + // Try to compute scheduling information.
>> + const MCSubtargetInfo *STI = DC->getSubtargetInfo();
>> + const MCSchedModel *SCModel = STI->getSchedModel();
>> + const int NoInformationAvailable = -1;
>> +
>> + // Check if we have a scheduling model for instructions.
>> + if (!SCModel || !SCModel->hasInstrSchedModel())
>> + return NoInformationAvailable;
>> +
>> + // Get the scheduling class of the requested instruction.
>> + const MCInstrDesc& Desc =
>> DC->getInstrInfo()->get(Inst.getOpcode());
>> + unsigned SCClass = Desc.getSchedClass();
>> + const MCSchedClassDesc *SCDesc =
>> SCModel->getSchedClassDesc(SCClass);
>> + if (!SCDesc || !SCDesc->isValid())
>> + return NoInformationAvailable;
>> +
>> + // Compute output latency.
>> + int Latency = 0;
>> + for (unsigned DefIdx = 0, DefEnd =
>> SCDesc->NumWriteLatencyEntries;
>> + DefIdx != DefEnd; ++DefIdx) {
>> + // Lookup the definition's write latency in SubtargetInfo.
>> + const MCWriteLatencyEntry *WLEntry =
>> STI->getWriteLatencyEntry(SCDesc,
>> +
>> DefIdx);
>> + Latency = std::max(Latency, WLEntry->Cycles);
>> + }
>> +
>> + return Latency;
>> +}
>> +
>> +
>> +/// \brief Emits latency information in DC->CommentStream for \p
>> Inst, based
>> +/// on the information available in \p DC.
>> +static void emitLatency(LLVMDisasmContext *DC, const MCInst
>> &Inst) {
>> + int Latency = getLatency(DC, Inst);
>> +
>> + // Report only interesting latency.
>> + if (Latency < 2)
>> + return;
>> +
>> + DC->CommentStream << "Latency: " << Latency << '\n';
>> +}
>> +
>> //
>> // LLVMDisasmInstruction() disassembles a single instruction using
>> the
>> // disassembler context specified in the parameter DC. The bytes
>> of
>> the
>> @@ -217,6 +263,9 @@ size_t LLVMDisasmInstruction(LLVMDisasmC
>> formatted_raw_ostream FormattedOS(OS);
>> IP->printInst(&Inst, FormattedOS, AnnotationsStr);
>>
>> + if (DC->getOptions() & LLVMDisassembler_Option_PrintLatency)
>> + emitLatency(DC, Inst);
>> +
>> emitComments(DC, FormattedOS);
>>
>> assert(OutStringSize != 0 && "Output buffer cannot be zero
>> size");
>> @@ -239,12 +288,14 @@ int LLVMSetDisasmOptions(LLVMDisasmConte
>> LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
>> MCInstPrinter *IP = DC->getIP();
>> IP->setUseMarkup(1);
>> + DC->addOptions(LLVMDisassembler_Option_UseMarkup);
>> Options &= ~LLVMDisassembler_Option_UseMarkup;
>> }
>> if (Options & LLVMDisassembler_Option_PrintImmHex){
>> LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
>> MCInstPrinter *IP = DC->getIP();
>> IP->setPrintImmHex(1);
>> + DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
>> Options &= ~LLVMDisassembler_Option_PrintImmHex;
>> }
>> if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
>> @@ -260,6 +311,7 @@ int LLVMSetDisasmOptions(LLVMDisasmConte
>> AsmPrinterVariant, *MAI, *MII, *MRI, *STI);
>> if (IP) {
>> DC->setIP(IP);
>> +
>> DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
>> Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
>> }
>> }
>> @@ -267,7 +319,13 @@ int LLVMSetDisasmOptions(LLVMDisasmConte
>> LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
>> MCInstPrinter *IP = DC->getIP();
>> IP->setCommentStream(DC->CommentStream);
>> + DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
>> Options &= ~LLVMDisassembler_Option_SetInstrComments;
>> }
>> + if (Options & LLVMDisassembler_Option_PrintLatency) {
>> + LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
>> + DC->addOptions(LLVMDisassembler_Option_PrintLatency);
>> + Options &= ~LLVMDisassembler_Option_PrintLatency;
>> + }
>> return (Options == 0);
>> }
>>
>> Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.h?rev=191859&r1=191858&r2=191859&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.h (original)
>> +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.h Wed Oct 2
>> 17:07:57 2013
>> @@ -73,6 +73,8 @@ private:
>> llvm::OwningPtr<const llvm::MCDisassembler> DisAsm;
>> // The instruction printer for the target architecture.
>> llvm::OwningPtr<llvm::MCInstPrinter> IP;
>> + // The options used to set up the disassembler.
>> + uint64_t Options;
>>
>> public:
>> // Comment stream and backing vector.
>> @@ -90,6 +92,7 @@ public:
>> MCInstPrinter *iP) : TripleName(tripleName),
>> DisInfo(disInfo), TagType(tagType),
>> GetOpInfo(getOpInfo),
>> SymbolLookUp(symbolLookUp),
>> TheTarget(theTarget),
>> + Options(0),
>> CommentStream(CommentsToEmit) {
>> MAI.reset(mAI);
>> MRI.reset(mRI);
>> @@ -114,6 +117,8 @@ public:
>> const MCSubtargetInfo *getSubtargetInfo() const { return
>> MSI.get(); }
>> MCInstPrinter *getIP() { return IP.get(); }
>> void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); }
>> + uint64_t getOptions() const { return Options; }
>> + void addOptions(uint64_t Options) { this->Options |= Options; }
>> };
>>
>> } // namespace llvm
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>> --
>> Hal Finkel
>> Assistant Computational Scientist
>> Leadership Computing Facility
>> Argonne National Laboratory
>>
>>
>>
>> --
>> Hal Finkel
>> Assistant Computational Scientist
>> Leadership Computing Facility
>> Argonne National Laboratory
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>
> --
> Hal Finkel
> Assistant Computational Scientist
> Leadership Computing Facility
> Argonne National Laboratory
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