[llvm] r191733 - AVX-512: Added X86vzmovl patterns
Elena Demikhovsky
elena.demikhovsky at intel.com
Tue Oct 1 01:38:02 PDT 2013
Author: delena
Date: Tue Oct 1 03:38:02 2013
New Revision: 191733
URL: http://llvm.org/viewvc/llvm-project?rev=191733&view=rev
Log:
AVX-512: Added X86vzmovl patterns
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/test/CodeGen/X86/avx512-mov.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=191733&r1=191732&r2=191733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Oct 1 03:38:02 2013
@@ -1467,6 +1467,10 @@ let Predicates = [HasAVX512] in {
let AddedComplexity = 20 in {
def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
(VMOVDI2PDIZrm addr:$src)>;
+ def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
+ (VMOV64toPQIZrr GR64:$src)>;
+ def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
+ (VMOVDI2PDIZrr GR32:$src)>;
def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
(VMOVDI2PDIZrm addr:$src)>;
@@ -1477,6 +1481,7 @@ let Predicates = [HasAVX512] in {
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
(VMOVZPQILo2PQIZrr VR128X:$src)>;
}
+
// Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
(v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
Modified: llvm/trunk/test/CodeGen/X86/avx512-mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mov.ll?rev=191733&r1=191732&r2=191733&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-mov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-mov.ll Tue Oct 1 03:38:02 2013
@@ -100,3 +100,19 @@ define <2 x double> @test12(double* %x)
%res = insertelement <2 x double>zeroinitializer, double %y, i32 0
ret <2 x double>%res
}
+
+; CHECK-LABEL: @test13
+; CHECK: vmovqz %rdi
+; CHECK: ret
+define <2 x i64> @test13(i64 %x) {
+ %res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0
+ ret <2 x i64>%res
+}
+
+; CHECK-LABEL: @test14
+; CHECK: vmovdz %edi
+; CHECK: ret
+define <4 x i32> @test14(i32 %x) {
+ %res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0
+ ret <4 x i32>%res
+}
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