[llvm] r191684 - [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR

[Jack Carter]

Author: jacksprat
Date: Mon Sep 30 12:43:04 2013
New Revision: 191684

URL: http://llvm.org/viewvc/llvm-project?rev=191684&view=rev
Log:
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
 and not an MSA register

Patch by Matheus Almeida

Added:
    llvm/trunk/test/MC/Mips/msa/test_2r.s
Modified:
    llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=191684&r1=191683&r2=191684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Mon Sep 30 12:43:04 2013
@@ -45,6 +45,17 @@ class MSA_BIT_D_FMT<bits<3> major, bits<
   let Inst{5-0} = minor;
 }
 
+class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
+  bits<5> rs;
+  bits<5> wd;
+
+  let Inst{25-18} = major;
+  let Inst{17-16} = df;
+  let Inst{15-11} = rs;
+  let Inst{10-6} = wd;
+  let Inst{5-0} = minor;
+}
+
 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
   let Inst{25-18} = major;
   let Inst{17-16} = df;

Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=191684&r1=191683&r2=191684&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Mon Sep 30 12:43:04 2013
@@ -602,9 +602,9 @@ class FFQL_D_ENC : MSA_2RF_FMT<0b1100110
 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
 
-class FILL_B_ENC : MSA_2R_FMT<0b11000000, 0b00, 0b011110>;
-class FILL_H_ENC : MSA_2R_FMT<0b11000000, 0b01, 0b011110>;
-class FILL_W_ENC : MSA_2R_FMT<0b11000000, 0b10, 0b011110>;
+class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
+class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
+class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
 
 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
@@ -1148,13 +1148,13 @@ class MSA_2R_DESC_BASE<string instr_asm,
 }
 
 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
-                            SDPatternOperator OpNode, RegisterClass RCWD,
-                            RegisterClass RCWS = RCWD,
+                            SDPatternOperator OpNode, RegisterOperand ROWD,
+                            RegisterOperand ROWS = ROWD,
                             InstrItinClass itin = NoItinerary> {
-  dag OutOperandList = (outs RCWD:$wd);
-  dag InOperandList = (ins RCWS:$ws);
-  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
-  list<dag> Pattern = [(set RCWD:$wd, (VT (OpNode RCWS:$ws)))];
+  dag OutOperandList = (outs ROWD:$wd);
+  dag InOperandList = (ins ROWS:$rs);
+  string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
+  list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROWS:$rs)))];
   InstrItinClass Itinerary = itin;
 }
 
@@ -1784,12 +1784,12 @@ class FFQR_W_DESC : MSA_2RF_DESC_BASE<"f
 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
                                       MSA128DOpnd, MSA128WOpnd>;
 
-class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,  MSA128B,
-                                          GPR32>;
-class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, MSA128H,
-                                          GPR32>;
-class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, MSA128W,
-                                          GPR32>;
+class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
+                                          MSA128BOpnd, GPR32Opnd>;
+class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
+                                          MSA128HOpnd, GPR32Opnd>;
+class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
+                                          MSA128WOpnd, GPR32Opnd>;
 
 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;

Added: llvm/trunk/test/MC/Mips/msa/test_2r.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/msa/test_2r.s?rev=191684&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/msa/test_2r.s (added)
+++ llvm/trunk/test/MC/Mips/msa/test_2r.s Mon Sep 30 12:43:04 2013
@@ -0,0 +1,15 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
+#
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
+#
+# CHECK:        fill.b  $w30, $9                # encoding: [0x7b,0x00,0x4f,0x9e]
+# CHECK:        fill.h  $w31, $23               # encoding: [0x7b,0x01,0xbf,0xde]
+# CHECK:        fill.w  $w16, $24               # encoding: [0x7b,0x02,0xc4,0x1e]
+
+# CHECKOBJDUMP:        fill.b  $w30, $9
+# CHECKOBJDUMP:        fill.h  $w31, $23
+# CHECKOBJDUMP:        fill.w  $w16, $24
+
+                fill.b  $w30, $9
+                fill.h  $w31, $23
+                fill.w  $w16, $24