[llvm] r191600 - SelectionDAG: Clean up LegalizeSetCCCondCode() function

[Charles Davis]

On Sep 27, 2013, at 8:50 PM, Tom Stellard wrote:
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=191600&r1=191599&r2=191600&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Sep 27 21:50:32 2013
> @@ -95,7 +95,7 @@ private:
>                                      SDValue N1, SDValue N2,
>                                      ArrayRef<int> Mask) const;
> 
> -  void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
> +  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
>                              SDLoc dl);
> 
>   SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
> @@ -1596,9 +1596,14 @@ void SelectionDAGLegalize::ExpandDYNAMIC
> }
> 
> /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
> -/// condition code CC on the current target. This routine expands SETCC with
> -/// illegal condition code into AND / OR of multiple SETCC values.
> -void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
> +/// condition code CC on the current target.
> +/// If the SETCC has been legalized using AND / OR, then the legalized node
> +/// will be stored in LHS and RHS and CC will be set to SDValue().
This isn't quite true (according to the behavior of the function, anyway): In this case, only LHS gets set to the legalized node; both RHS and CC get set to empty (SDValue()).
> +/// If the SETCC has been legalized by using getSetCCSwappedOperands(),
> +/// then the values of LHS and RHS will be swapped and CC will be set to the
> +/// new condition.
> +/// \returns true if the SetCC has been legalized, false if it hasn't.
> +bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
>                                                  SDValue &LHS, SDValue &RHS,
>                                                  SDValue &CC,
>                                                  SDLoc dl) {
> @@ -1659,10 +1664,9 @@ void SelectionDAGLegalize::LegalizeSetCC
>         // different manner of supporting expanding these cases.
>         llvm_unreachable("Don't know how to expand this condition!");
>       }
> -      LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
> -      RHS = SDValue();
> -      CC = SDValue();
> -      return;
> +      std::swap(LHS, RHS);
> +      CC = DAG.getCondCode(InvCC);
> +      return true;
>     }
> 
>     SDValue SetCC1, SetCC2;
> @@ -1679,9 +1683,10 @@ void SelectionDAGLegalize::LegalizeSetCC
>     LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
>     RHS = SDValue();
>     CC  = SDValue();
> -    break;
> +    return true;
>   }
>   }
> +  return false;
> }
> 
> /// EmitStackConvert - Emit a store/load combination to the stack.  This stores
> @@ -3620,10 +3625,16 @@ void SelectionDAGLegalize::ExpandNode(SD
>     Tmp1 = Node->getOperand(0);
>     Tmp2 = Node->getOperand(1);
>     Tmp3 = Node->getOperand(2);
> -    LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
> +    bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
> +                                           Tmp3, dl);
> +
> +    if (Legalized) {
> +      // If we exapanded the SETCC by swapping LHS and RHS, create a new SETCC
> +      // node..
Too many periods here.

Chip