[llvm] r191610 - Fix spelling intruction -> instruction.
Robert Wilhelm
robert.wilhelm at gmx.net
Sat Sep 28 04:46:16 PDT 2013
Author: row
Date: Sat Sep 28 06:46:15 2013
New Revision: 191610
URL: http://llvm.org/viewvc/llvm-project?rev=191610&view=rev
Log:
Fix spelling intruction -> instruction.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/StackColoring.cpp
llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp
llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp
llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll
llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sat Sep 28 06:46:15 2013
@@ -718,7 +718,7 @@ void ScheduleDAGRRList::ScheduleNodeBott
// indicate the scheduled cycle.
SU->setHeightToAtLeast(CurCycle);
- // Reserve resources for the scheduled intruction.
+ // Reserve resources for the scheduled instruction.
EmitNode(SU);
Sequence.push_back(SU);
Modified: llvm/trunk/lib/CodeGen/StackColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackColoring.cpp?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackColoring.cpp Sat Sep 28 06:46:15 2013
@@ -170,7 +170,7 @@ private:
/// slots to use the joint slots.
void remapInstructions(DenseMap<int, int> &SlotRemap);
- /// The input program may contain intructions which are not inside lifetime
+ /// The input program may contain instructions which are not inside lifetime
/// markers. This can happen due to a bug in the compiler or due to a bug in
/// user code (for example, returning a reference to a local variable).
/// This procedure checks all of the instructions in the function and
Modified: llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp Sat Sep 28 06:46:15 2013
@@ -36,7 +36,7 @@ bool NVPTXSplitBBatBar::runOnFunction(Fu
BasicBlock::iterator II = IB;
BasicBlock::iterator IE = BI->end();
- // Skit the first intruction. No splitting is needed at this
+ // Skit the first instruction. No splitting is needed at this
// point even if this is a bar.
while (II != IE) {
if (IntrinsicInst *inst = dyn_cast<IntrinsicInst>(II)) {
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Sep 28 06:46:15 2013
@@ -9442,7 +9442,7 @@ SDValue X86TargetLowering::EmitTest(SDVa
unsigned NumOperands = 0;
// Truncate operations may prevent the merge of the SETCC instruction
- // and the arithmetic intruction before it. Attempt to truncate the operands
+ // and the arithmetic instruction before it. Attempt to truncate the operands
// of the arithmetic instruction and use a reduced bit-width instruction.
bool NeedTruncation = false;
SDValue ArithOp = Op;
@@ -11319,7 +11319,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S
case Intrinsic::x86_avx2_permd:
case Intrinsic::x86_avx2_permps:
// Operands intentionally swapped. Mask is last operand to intrinsic,
- // but second operand for node/intruction.
+ // but second operand for node/instruction.
return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
Op.getOperand(2), Op.getOperand(1));
Modified: llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp Sat Sep 28 06:46:15 2013
@@ -29,7 +29,7 @@
using namespace llvm;
-STATISTIC(IfHandled, "Number of 'expect' intrinsic intructions handled");
+STATISTIC(IfHandled, "Number of 'expect' intrinsic instructions handled");
static cl::opt<uint32_t>
LikelyBranchWeight("likely-branch-weight", cl::Hidden, cl::init(64),
Modified: llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp (original)
+++ llvm/trunk/lib/Transforms/Vectorize/BBVectorize.cpp Sat Sep 28 06:46:15 2013
@@ -533,7 +533,7 @@ namespace {
default: break;
case Instruction::GetElementPtr:
// We mark this instruction as zero-cost because scalar GEPs are usually
- // lowered to the intruction addressing mode. At the moment we don't
+ // lowered to the instruction addressing mode. At the moment we don't
// generate vector GEPs.
return 0;
case Instruction::Br:
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll Sat Sep 28 06:46:15 2013
@@ -5,7 +5,7 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
-; Altivec does not provides an sext intruction, so it expands
+; Altivec does not provides an sext instruction, so it expands
; a set of vector stores (stvx), bytes load/sign expand/store
; (lbz/stb), and a final vector load (lvx) to load the result
; extended vector.
Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll Sat Sep 28 06:46:15 2013
@@ -40,7 +40,7 @@ entry:
; CHECK: pop
; CHECK: pop
; Do not convert into single stream code. BranchProbability Analysis assumes
-; that branches which goes to "ret" intruction have lower probabilities.
+; that branches which goes to "ret" instruction have lower probabilities.
switch i32 undef, label %bb7 [
i32 37, label %bb43
i32 48, label %bb5
Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt?rev=191610&r1=191609&r2=191610&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt Sat Sep 28 06:46:15 2013
@@ -183,7 +183,7 @@
# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
-# The instruction is UNPREDICTABLE, and is not a valid intruction.
+# The instruction is UNPREDICTABLE, and is not a valid instruction.
#
# See also
# A8.6.88 LSL (immediate)
@@ -201,7 +201,7 @@
# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
-# The instruction is UNPREDICTABLE, and is not a valid intruction.
+# The instruction is UNPREDICTABLE, and is not a valid instruction.
#
# See also
# A8.6.97 MOV (register)
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