[llvm] r191421 - PPC: Do not introduce ISD nodes for fctid and fctiw
Chandler Carruth
chandlerc at google.com
Wed Sep 25 22:29:06 PDT 2013
On Thu, Sep 26, 2013 at 12:22 AM, David Majnemer
<david.majnemer at gmail.com>wrote:
> Author: majnemer
> Date: Thu Sep 26 00:22:11 2013
> New Revision: 191421
>
> URL: http://llvm.org/viewvc/llvm-project?rev=191421&view=rev
> Log:
> PPC: Do not introduce ISD nodes for fctid and fctiw
>
Both a test case and an explanation for the commit log seem in order here.
>
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=191421&r1=191420&r2=191421&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Sep 26 00:22:11
> 2013
> @@ -42,10 +42,10 @@ namespace llvm {
> /// unsigned integers and single-precision outputs.
> FCFIDU, FCFIDS, FCFIDUS,
>
> - /// FCTI[D,W]Z? - The FCTID, FCTIDZ, FCTIW and FCTIWZ instructions,
> - /// taking an f32 or f64 operand, producing an f64 value containing
> the
> - /// integer representation of that FP value.
> - FCTID, FCTIDZ, FCTIW, FCTIWZ,
> + /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32
> or f64
> + /// operand, producing an f64 value containing the integer
> representation
> + /// of that FP value.
> + FCTIDZ, FCTIWZ,
>
> /// Newer FCTI[D,W]UZ floating-point-to-integer conversion
> instructions for
> /// unsigned integers.
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=191421&r1=191420&r2=191421&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Thu Sep 26 00:22:11 2013
> @@ -970,7 +970,7 @@ defm FCFID : XForm_26r<63, 846, (outs f
> [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
> defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctid", "$frD, $frB", FPGeneral,
> - [(set f64:$frD, (PPCfctid f64:$frB))]>, isPPC64;
> + []>, isPPC64;
> defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctidz", "$frD, $frB", FPGeneral,
> [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=191421&r1=191420&r2=191421&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Sep 26 00:22:11 2013
> @@ -69,9 +69,7 @@ def PPCfcfid : SDNode<"PPCISD::FCFID",
> def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
> def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
> def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
> -def PPCfctid : SDNode<"PPCISD::FCTID", SDTFPUnaryOp, []>;
> def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
> -def PPCfctiw : SDNode<"PPCISD::FCTIW", SDTFPUnaryOp, []>;
> def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
> def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
> def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
> @@ -1696,7 +1694,7 @@ let Uses = [RM] in {
> let neverHasSideEffects = 1 in {
> defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctiw", "$frD, $frB", FPGeneral,
> - [(set f64:$frD, (PPCfctiw f64:$frB))]>;
> + []>;
> defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctiwz", "$frD, $frB", FPGeneral,
> [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
>
>
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