[llvm] r191419 - PPC: Add support for fctid and fctiw
Hal Finkel
hfinkel at anl.gov
Wed Sep 25 21:48:07 PDT 2013
----- Original Message -----
> Author: majnemer
> Date: Wed Sep 25 23:11:24 2013
> New Revision: 191419
>
> URL: http://llvm.org/viewvc/llvm-project?rev=191419&view=rev
> Log:
> PPC: Add support for fctid and fctiw
>
> Encodings were checked against the Power ISA documents and double
> checked against binutils.
>
> This fixes PR17350.
>
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=191419&r1=191418&r2=191419&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Wed Sep 25
> 23:11:24 2013
> @@ -42,10 +42,10 @@ namespace llvm {
> /// unsigned integers and single-precision outputs.
> FCFIDU, FCFIDS, FCFIDUS,
>
> - /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an
> f32 or f64
> - /// operand, producing an f64 value containing the integer
> representation
> - /// of that FP value.
> - FCTIDZ, FCTIWZ,
> + /// FCTI[D,W]Z? - The FCTID, FCTIDZ, FCTIW and FCTIWZ
> instructions,
> + /// taking an f32 or f64 operand, producing an f64 value
> containing the
> + /// integer representation of that FP value.
> + FCTID, FCTIDZ, FCTIW, FCTIWZ,
Why did you add these ISD nodes and the associated TableGen patterns? Is there a follow-up commit coming with associated code generation support? If not, then you only need the instruction definitions to get assembler support (and we should remove the ISD nodes unless and until we need them).
Thanks,
Hal
>
> /// Newer FCTI[D,W]UZ floating-point-to-integer conversion
> instructions for
> /// unsigned integers.
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=191419&r1=191418&r2=191419&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Wed Sep 25
> 23:11:24 2013
> @@ -968,6 +968,9 @@ let PPC970_Unit = 3, neverHasSideEffects
> defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
> "fcfid", "$frD, $frB", FPGeneral,
> [(set f64:$frD, (PPCfcfid f64:$frB))]>,
> isPPC64;
> +defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
> + "fctid", "$frD, $frB", FPGeneral,
> + [(set f64:$frD, (PPCfctid f64:$frB))]>,
> isPPC64;
> defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctidz", "$frD, $frB", FPGeneral,
> [(set f64:$frD, (PPCfctidz f64:$frB))]>,
> isPPC64;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=191419&r1=191418&r2=191419&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed Sep 25 23:11:24
> 2013
> @@ -69,7 +69,9 @@ def PPCfcfid : SDNode<"PPCISD::FCFID",
> def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
> def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
> def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
> +def PPCfctid : SDNode<"PPCISD::FCTID", SDTFPUnaryOp, []>;
> def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
> +def PPCfctiw : SDNode<"PPCISD::FCTIW", SDTFPUnaryOp, []>;
> def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
> def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
> def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
> @@ -1692,6 +1694,9 @@ let isCompare = 1, neverHasSideEffects =
>
> let Uses = [RM] in {
> let neverHasSideEffects = 1 in {
> + defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
> + "fctiw", "$frD, $frB", FPGeneral,
> + [(set f64:$frD, (PPCfctiw f64:$frB))]>;
> defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
> "fctiwz", "$frD, $frB", FPGeneral,
> [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
>
> Modified: llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s?rev=191419&r1=191418&r2=191419&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s (original)
> +++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-fp.s Wed Sep 25
> 23:11:24 2013
> @@ -173,8 +173,10 @@
> # CHECK: frsp. 2, 3 # encoding:
> [0xfc,0x40,0x18,0x19]
> frsp. 2, 3
>
> -# FIXME: fctid 2, 3
> -# FIXME: fctid. 2, 3
> +# CHECK: fctid 2, 3 # encoding:
> [0xfc,0x40,0x1e,0x5c]
> + fctid 2, 3
> +# CHECK: fctid. 2, 3 # encoding:
> [0xfc,0x40,0x1e,0x5d]
> + fctid. 2, 3
> # CHECK: fctidz 2, 3 # encoding:
> [0xfc,0x40,0x1e,0x5e]
> fctidz 2, 3
> # CHECK: fctidz. 2, 3 # encoding:
> [0xfc,0x40,0x1e,0x5f]
> @@ -185,8 +187,10 @@
> fctiduz 2, 3
> # CHECK: fctiduz. 2, 3 # encoding:
> [0xfc,0x40,0x1f,0x5f]
> fctiduz. 2, 3
> -# FIXME: fctiw 2, 3
> -# FIXME: fctiw. 2, 3
> +# CHECK: fctiw 2, 3 # encoding:
> [0xfc,0x40,0x18,0x1c]
> + fctiw 2, 3
> +# CHECK: fctiw. 2, 3 # encoding:
> [0xfc,0x40,0x18,0x1d]
> + fctiw. 2, 3
> # CHECK: fctiwz 2, 3 # encoding:
> [0xfc,0x40,0x18,0x1e]
> fctiwz 2, 3
> # CHECK: fctiwz. 2, 3 # encoding:
> [0xfc,0x40,0x18,0x1f]
>
>
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--
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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