[PATCH] [AArch64] Add Register Operand to constrain registers to V0-V15 range

[Ana Pazos]

Hi Tim, Jiangning,

I noted that in Jiangning's latest patch below the constraining of V0-V15 range was done by duplicating the FPR64 and FPR128 register class and truncating them to indexes 0-15.

I also needed such constraint in the implementation of Scalar-by-elem arithmetic instructions. 

But I implemented it differently, I used RegisterOperand class instead.

See if you find this solution better and if it satisfies the instructions Jiangning implemented.

Thanks,
Ana.



-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jiangning Liu
Sent: Wednesday, September 25, 2013 2:27 AM
To: llvm-commits at cs.uiuc.edu; cfe-commits at cs.uiuc.edu
Subject: Re: [PATCH] Implement aarch64 neon instruction class AdvSIMD (by element) - LLVM

Jiangning added you to the CC list for the revision "Implement aarch64 neon instruction class AdvSIMD (by element) - LLVM".

Hi t.p.northover,

http://llvm-reviews.chandlerc.com/D1753

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/AArch64/AArch64InstrFormats.td
  lib/Target/AArch64/AArch64InstrNEON.td
  lib/Target/AArch64/AArch64RegisterInfo.td
  lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  test/CodeGen/AArch64/neon-2velem.ll
  test/MC/AArch64/neon-2velem.s
  test/MC/AArch64/neon-diagnostics.s
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