[llvm] r191393 - Teach DAGCombiner how to canonicalize dags according to the rule
Andrea Di Biagio
Andrea_DiBiagio at sn.scee.net
Wed Sep 25 12:01:01 PDT 2013
Author: adibiagio
Date: Wed Sep 25 14:01:01 2013
New Revision: 191393
URL: http://llvm.org/viewvc/llvm-project?rev=191393&view=rev
Log:
Teach DAGCombiner how to canonicalize dags according to the rule
(shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).
The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.
This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.
Added:
llvm/trunk/test/CodeGen/X86/dagcombine-shifts.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=191393&r1=191392&r2=191393&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Sep 25 14:01:01 2013
@@ -3748,6 +3748,26 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
}
}
+ // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
+ // Only fold this if the inner zext has no other uses to avoid increasing
+ // the total number of instructions.
+ if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
+ N0.getOperand(0).getOpcode() == ISD::SRL &&
+ isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
+ uint64_t c1 =
+ cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
+ if (c1 < VT.getSizeInBits()) {
+ uint64_t c2 = N1C->getZExtValue();
+ if (c1 == c2) {
+ SDValue NewOp0 = N0.getOperand(0);
+ EVT ShiftVT = NewOp0.getValueType();
+ SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), ShiftVT,
+ NewOp0, DAG.getConstant(c2, ShiftVT));
+ return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
+ }
+ }
+ }
+
// fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
// (and (srl x, (sub c1, c2), MASK)
// Only fold this if the inner shift has no other uses -- if it does, folding
Added: llvm/trunk/test/CodeGen/X86/dagcombine-shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dagcombine-shifts.ll?rev=191393&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dagcombine-shifts.ll (added)
+++ llvm/trunk/test/CodeGen/X86/dagcombine-shifts.ll Wed Sep 25 14:01:01 2013
@@ -0,0 +1,181 @@
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
+
+; fold (shl (zext (lshr (A, X))), X) -> (zext (shl (lshr (A, X)), X))
+
+; Canolicalize the sequence shl/zext/lshr performing the zeroextend
+; as the last instruction of the sequence.
+; This will help DAGCombiner to identify and then fold the sequence
+; of shifts into a single AND.
+; This transformation is profitable if the shift amounts are the same
+; and if there is only one use of the zext.
+
+define i16 @fun1(i8 zeroext %v) {
+entry:
+ %shr = lshr i8 %v, 4
+ %ext = zext i8 %shr to i16
+ %shl = shl i16 %ext, 4
+ ret i16 %shl
+}
+
+; CHECK-LABEL: @fun1
+; CHECK: and
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: ret
+
+define i32 @fun2(i8 zeroext %v) {
+entry:
+ %shr = lshr i8 %v, 4
+ %ext = zext i8 %shr to i32
+ %shl = shl i32 %ext, 4
+ ret i32 %shl
+}
+
+; CHECK-LABEL: @fun2
+; CHECK: and
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: ret
+
+define i32 @fun3(i16 zeroext %v) {
+entry:
+ %shr = lshr i16 %v, 4
+ %ext = zext i16 %shr to i32
+ %shl = shl i32 %ext, 4
+ ret i32 %shl
+}
+
+; CHECK-LABEL: @fun3
+; CHECK: and
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: ret
+
+define i64 @fun4(i8 zeroext %v) {
+entry:
+ %shr = lshr i8 %v, 4
+ %ext = zext i8 %shr to i64
+ %shl = shl i64 %ext, 4
+ ret i64 %shl
+}
+
+; CHECK-LABEL: @fun4
+; CHECK: and
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: ret
+
+define i64 @fun5(i16 zeroext %v) {
+entry:
+ %shr = lshr i16 %v, 4
+ %ext = zext i16 %shr to i64
+ %shl = shl i64 %ext, 4
+ ret i64 %shl
+}
+
+; CHECK-LABEL: @fun5
+; CHECK: and
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: ret
+
+define i64 @fun6(i32 zeroext %v) {
+entry:
+ %shr = lshr i32 %v, 4
+ %ext = zext i32 %shr to i64
+ %shl = shl i64 %ext, 4
+ ret i64 %shl
+}
+
+; CHECK-LABEL: @fun6
+; CHECK: and
+; CHECK-NOT: shr
+; CHECK-NOT: shl
+; CHECK: ret
+
+; Don't fold the pattern if we use arithmetic shifts.
+
+define i64 @fun7(i8 zeroext %v) {
+entry:
+ %shr = ashr i8 %v, 4
+ %ext = zext i8 %shr to i64
+ %shl = shl i64 %ext, 4
+ ret i64 %shl
+}
+
+; CHECK-LABEL: @fun7
+; CHECK: sar
+; CHECK: shl
+; CHECK: ret
+
+define i64 @fun8(i16 zeroext %v) {
+entry:
+ %shr = ashr i16 %v, 4
+ %ext = zext i16 %shr to i64
+ %shl = shl i64 %ext, 4
+ ret i64 %shl
+}
+
+; CHECK-LABEL: @fun8
+; CHECK: sar
+; CHECK: shl
+; CHECK: ret
+
+define i64 @fun9(i32 zeroext %v) {
+entry:
+ %shr = ashr i32 %v, 4
+ %ext = zext i32 %shr to i64
+ %shl = shl i64 %ext, 4
+ ret i64 %shl
+}
+
+; CHECK-LABEL: @fun9
+; CHECK: sar
+; CHECK: shl
+; CHECK: ret
+
+; Don't fold the pattern if there is more than one use of the
+; operand in input to the shift left.
+
+define i64 @fun10(i8 zeroext %v) {
+entry:
+ %shr = lshr i8 %v, 4
+ %ext = zext i8 %shr to i64
+ %shl = shl i64 %ext, 4
+ %add = add i64 %shl, %ext
+ ret i64 %add
+}
+
+; CHECK-LABEL: @fun10
+; CHECK: shr
+; CHECK: shl
+; CHECK: ret
+
+define i64 @fun11(i16 zeroext %v) {
+entry:
+ %shr = lshr i16 %v, 4
+ %ext = zext i16 %shr to i64
+ %shl = shl i64 %ext, 4
+ %add = add i64 %shl, %ext
+ ret i64 %add
+}
+
+; CHECK-LABEL: @fun11
+; CHECK: shr
+; CHECK: shl
+; CHECK: ret
+
+define i64 @fun12(i32 zeroext %v) {
+entry:
+ %shr = lshr i32 %v, 4
+ %ext = zext i32 %shr to i64
+ %shl = shl i64 %ext, 4
+ %add = add i64 %shl, %ext
+ ret i64 %add
+}
+
+; CHECK-LABEL: @fun12
+; CHECK: shr
+; CHECK: shl
+; CHECK: ret
+
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