[llvm] r191194 - [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)
Daniel Sanders
daniel.sanders at imgtec.com
Mon Sep 23 05:57:43 PDT 2013
Author: dsanders
Date: Mon Sep 23 07:57:42 2013
New Revision: 191194
URL: http://llvm.org/viewvc/llvm-project?rev=191194&view=rev
Log:
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics)
Modified:
llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
llvm/trunk/test/CodeGen/Mips/msa/vec.ll
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td?rev=191194&r1=191193&r2=191194&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrInfo.td Mon Sep 23 07:57:42 2013
@@ -953,6 +953,12 @@ class MSA_VEC_DESC_BASE<string instr_asm
InstrItinClass Itinerary = itin;
}
+class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterClass RCWD,
+ RegisterClass RCWS = RCWD,
+ RegisterClass RCWT = RCWD> :
+ MipsPseudo<(outs RCWD:$wd), (ins RCWS:$ws, RCWT:$wt),
+ [(set RCWD:$wd, (OpNode RCWS:$ws, RCWT:$wt))]>;
+
class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128B>,
IsCommutable;
class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128H>,
@@ -999,7 +1005,10 @@ class ADDVI_H_DESC : MSA_I5_DESC_BASE<"a
class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", int_mips_addvi_w, MSA128W>;
class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", int_mips_addvi_d, MSA128D>;
-class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", int_mips_and_v, MSA128B>;
+class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128B>;
+class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128H>;
+class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128W>;
+class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128D>;
class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", int_mips_andi_b, MSA128B>;
@@ -1724,7 +1733,10 @@ class NOR_V_DESC : MSA_VEC_DESC_BASE<"no
class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", int_mips_nori_b, MSA128B>;
-class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", int_mips_or_v, MSA128B>;
+class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128B>;
+class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128H>;
+class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128W>;
+class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128D>;
class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", int_mips_ori_b, MSA128B>;
@@ -1910,7 +1922,10 @@ class VSHF_H_DESC : MSA_3R_DESC_BASE<"vs
class VSHF_W_DESC : MSA_3R_DESC_BASE<"vshf.w", int_mips_vshf_w, MSA128W>;
class VSHF_D_DESC : MSA_3R_DESC_BASE<"vshf.d", int_mips_vshf_d, MSA128D>;
-class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", int_mips_xor_v, MSA128B>;
+class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128B>;
+class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128H>;
+class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128W>;
+class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128D>;
class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", int_mips_xori_b, MSA128B>;
@@ -1946,6 +1961,15 @@ def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
def AND_V : AND_V_ENC, AND_V_DESC;
+def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
+ PseudoInstExpansion<(AND_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
+def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
+ PseudoInstExpansion<(AND_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
+def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
+ PseudoInstExpansion<(AND_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
@@ -2478,6 +2502,15 @@ def NOR_V : NOR_V_ENC, NOR_V_DESC;
def NORI_B : NORI_B_ENC, NORI_B_DESC;
def OR_V : OR_V_ENC, OR_V_DESC;
+def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
+ PseudoInstExpansion<(OR_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
+def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
+ PseudoInstExpansion<(OR_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
+def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
+ PseudoInstExpansion<(OR_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
def ORI_B : ORI_B_ENC, ORI_B_DESC;
@@ -2626,6 +2659,15 @@ def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
def XOR_V : XOR_V_ENC, XOR_V_DESC;
+def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
+ PseudoInstExpansion<(XOR_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
+def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
+ PseudoInstExpansion<(XOR_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
+def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
+ PseudoInstExpansion<(XOR_V MSA128B:$wd,
+ MSA128B:$ws, MSA128B:$wt)>;
def XORI_B : XORI_B_ENC, XORI_B_DESC;
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=191194&r1=191193&r2=191194&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Mon Sep 23 07:57:42 2013
@@ -162,14 +162,17 @@ addMSAIntType(MVT::SimpleValueType Ty, c
setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
setOperationAction(ISD::ADD, Ty, Legal);
+ setOperationAction(ISD::AND, Ty, Legal);
setOperationAction(ISD::CTLZ, Ty, Legal);
setOperationAction(ISD::MUL, Ty, Legal);
+ setOperationAction(ISD::OR, Ty, Legal);
setOperationAction(ISD::SDIV, Ty, Legal);
setOperationAction(ISD::SHL, Ty, Legal);
setOperationAction(ISD::SRA, Ty, Legal);
setOperationAction(ISD::SRL, Ty, Legal);
setOperationAction(ISD::SUB, Ty, Legal);
setOperationAction(ISD::UDIV, Ty, Legal);
+ setOperationAction(ISD::XOR, Ty, Legal);
}
// Enable MSA support for the given floating-point type and Register class.
@@ -895,6 +898,8 @@ SDValue MipsSETargetLowering::lowerINTRI
case Intrinsic::mips_addv_w:
case Intrinsic::mips_addv_d:
return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
+ case Intrinsic::mips_and_v:
+ return lowerMSABinaryIntr(Op, DAG, ISD::AND);
case Intrinsic::mips_bnz_b:
case Intrinsic::mips_bnz_h:
case Intrinsic::mips_bnz_w:
@@ -959,6 +964,8 @@ SDValue MipsSETargetLowering::lowerINTRI
case Intrinsic::mips_nlzc_w:
case Intrinsic::mips_nlzc_d:
return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
+ case Intrinsic::mips_or_v:
+ return lowerMSABinaryIntr(Op, DAG, ISD::OR);
case Intrinsic::mips_sll_b:
case Intrinsic::mips_sll_h:
case Intrinsic::mips_sll_w:
@@ -979,6 +986,8 @@ SDValue MipsSETargetLowering::lowerINTRI
case Intrinsic::mips_subv_w:
case Intrinsic::mips_subv_d:
return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
+ case Intrinsic::mips_xor_v:
+ return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
}
}
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll?rev=191194&r1=191193&r2=191194&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitwise.ll Mon Sep 23 07:57:42 2013
@@ -1,5 +1,197 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+ ; CHECK: and_v16i8:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <16 x i8>* %b
+ ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <16 x i8> %1, %2
+ ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <16 x i8> %3, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v16i8
+}
+
+define void @and_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+ ; CHECK: and_v8i16:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <8 x i16>* %b
+ ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <8 x i16> %1, %2
+ ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <8 x i16> %3, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v8i16
+}
+
+define void @and_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+ ; CHECK: and_v4i32:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <4 x i32>* %b
+ ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <4 x i32> %1, %2
+ ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <4 x i32> %3, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v4i32
+}
+
+define void @and_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+ ; CHECK: and_v2i64:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <2 x i64>* %b
+ ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <2 x i64> %1, %2
+ ; CHECK-DAG: and.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <2 x i64> %3, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size and_v2i64
+}
+
+define void @or_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+ ; CHECK: or_v16i8:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <16 x i8>* %b
+ ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+ %3 = or <16 x i8> %1, %2
+ ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <16 x i8> %3, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v16i8
+}
+
+define void @or_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+ ; CHECK: or_v8i16:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <8 x i16>* %b
+ ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+ %3 = or <8 x i16> %1, %2
+ ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <8 x i16> %3, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v8i16
+}
+
+define void @or_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+ ; CHECK: or_v4i32:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <4 x i32>* %b
+ ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+ %3 = or <4 x i32> %1, %2
+ ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <4 x i32> %3, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v4i32
+}
+
+define void @or_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+ ; CHECK: or_v2i64:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <2 x i64>* %b
+ ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+ %3 = or <2 x i64> %1, %2
+ ; CHECK-DAG: or.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <2 x i64> %3, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size or_v2i64
+}
+
+define void @xor_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+ ; CHECK: xor_v16i8:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <16 x i8>* %b
+ ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+ %3 = xor <16 x i8> %1, %2
+ ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <16 x i8> %3, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v16i8
+}
+
+define void @xor_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+ ; CHECK: xor_v8i16:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <8 x i16>* %b
+ ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+ %3 = xor <8 x i16> %1, %2
+ ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <8 x i16> %3, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v8i16
+}
+
+define void @xor_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+ ; CHECK: xor_v4i32:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <4 x i32>* %b
+ ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+ %3 = xor <4 x i32> %1, %2
+ ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <4 x i32> %3, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v4i32
+}
+
+define void @xor_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+ ; CHECK: xor_v2i64:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <2 x i64>* %b
+ ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+ %3 = xor <2 x i64> %1, %2
+ ; CHECK-DAG: xor.v [[R3:\$w[0-9]+]], [[R1]], [[R2]]
+ store <2 x i64> %3, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size xor_v2i64
+}
+
define void @sll_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: sll_v16i8:
Modified: llvm/trunk/test/CodeGen/Mips/msa/vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/vec.ll?rev=191194&r1=191193&r2=191194&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/vec.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/vec.ll Mon Sep 23 07:57:42 2013
@@ -95,6 +95,72 @@ entry:
; ANYENDIAN: st.b
; ANYENDIAN: .size llvm_mips_and_v_d_test
;
+define void @and_v_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_and_v_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_and_v_b_ARG2
+ %2 = and <16 x i8> %0, %1
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_and_v_b_RES
+ ret void
+}
+
+; CHECK: and_v_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: and.v
+; CHECK: st.b
+; CHECK: .size and_v_b_test
+;
+define void @and_v_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_and_v_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_and_v_h_ARG2
+ %2 = and <8 x i16> %0, %1
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_and_v_h_RES
+ ret void
+}
+
+; CHECK: and_v_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: and.v
+; CHECK: st.h
+; CHECK: .size and_v_h_test
+;
+
+define void @and_v_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_and_v_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_and_v_w_ARG2
+ %2 = and <4 x i32> %0, %1
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_and_v_w_RES
+ ret void
+}
+
+; CHECK: and_v_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: and.v
+; CHECK: st.w
+; CHECK: .size and_v_w_test
+;
+
+define void @and_v_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_and_v_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_and_v_d_ARG2
+ %2 = and <2 x i64> %0, %1
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_and_v_d_RES
+ ret void
+}
+
+; CHECK: and_v_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: and.v
+; CHECK: st.d
+; CHECK: .size and_v_d_test
+;
@llvm_mips_bmnz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bmnz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
@llvm_mips_bmnz_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@@ -555,6 +621,72 @@ entry:
; ANYENDIAN: st.b
; ANYENDIAN: .size llvm_mips_or_v_d_test
;
+define void @or_v_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_or_v_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_or_v_b_ARG2
+ %2 = or <16 x i8> %0, %1
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_or_v_b_RES
+ ret void
+}
+
+; CHECK: or_v_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: or.v
+; CHECK: st.b
+; CHECK: .size or_v_b_test
+;
+define void @or_v_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_or_v_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_or_v_h_ARG2
+ %2 = or <8 x i16> %0, %1
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_or_v_h_RES
+ ret void
+}
+
+; CHECK: or_v_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: or.v
+; CHECK: st.h
+; CHECK: .size or_v_h_test
+;
+
+define void @or_v_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_or_v_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_or_v_w_ARG2
+ %2 = or <4 x i32> %0, %1
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_or_v_w_RES
+ ret void
+}
+
+; CHECK: or_v_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: or.v
+; CHECK: st.w
+; CHECK: .size or_v_w_test
+;
+
+define void @or_v_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_or_v_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_or_v_d_ARG2
+ %2 = or <2 x i64> %0, %1
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_or_v_d_RES
+ ret void
+}
+
+; CHECK: or_v_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: or.v
+; CHECK: st.d
+; CHECK: .size or_v_d_test
+;
@llvm_mips_xor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_xor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
@llvm_mips_xor_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@@ -647,6 +779,72 @@ entry:
; ANYENDIAN: st.b
; ANYENDIAN: .size llvm_mips_xor_v_d_test
;
+define void @xor_v_b_test() nounwind {
+entry:
+ %0 = load <16 x i8>* @llvm_mips_xor_v_b_ARG1
+ %1 = load <16 x i8>* @llvm_mips_xor_v_b_ARG2
+ %2 = xor <16 x i8> %0, %1
+ store <16 x i8> %2, <16 x i8>* @llvm_mips_xor_v_b_RES
+ ret void
+}
+
+; CHECK: xor_v_b_test:
+; CHECK: ld.b
+; CHECK: ld.b
+; CHECK: xor.v
+; CHECK: st.b
+; CHECK: .size xor_v_b_test
+;
+define void @xor_v_h_test() nounwind {
+entry:
+ %0 = load <8 x i16>* @llvm_mips_xor_v_h_ARG1
+ %1 = load <8 x i16>* @llvm_mips_xor_v_h_ARG2
+ %2 = xor <8 x i16> %0, %1
+ store <8 x i16> %2, <8 x i16>* @llvm_mips_xor_v_h_RES
+ ret void
+}
+
+; CHECK: xor_v_h_test:
+; CHECK: ld.h
+; CHECK: ld.h
+; CHECK: xor.v
+; CHECK: st.h
+; CHECK: .size xor_v_h_test
+;
+
+define void @xor_v_w_test() nounwind {
+entry:
+ %0 = load <4 x i32>* @llvm_mips_xor_v_w_ARG1
+ %1 = load <4 x i32>* @llvm_mips_xor_v_w_ARG2
+ %2 = xor <4 x i32> %0, %1
+ store <4 x i32> %2, <4 x i32>* @llvm_mips_xor_v_w_RES
+ ret void
+}
+
+; CHECK: xor_v_w_test:
+; CHECK: ld.w
+; CHECK: ld.w
+; CHECK: xor.v
+; CHECK: st.w
+; CHECK: .size xor_v_w_test
+;
+
+define void @xor_v_d_test() nounwind {
+entry:
+ %0 = load <2 x i64>* @llvm_mips_xor_v_d_ARG1
+ %1 = load <2 x i64>* @llvm_mips_xor_v_d_ARG2
+ %2 = xor <2 x i64> %0, %1
+ store <2 x i64> %2, <2 x i64>* @llvm_mips_xor_v_d_RES
+ ret void
+}
+
+; CHECK: xor_v_d_test:
+; CHECK: ld.d
+; CHECK: ld.d
+; CHECK: xor.v
+; CHECK: st.d
+; CHECK: .size xor_v_d_test
+;
declare <16 x i8> @llvm.mips.and.v(<16 x i8>, <16 x i8>) nounwind
declare <16 x i8> @llvm.mips.bmnz.v(<16 x i8>, <16 x i8>) nounwind
declare <16 x i8> @llvm.mips.bmz.v(<16 x i8>, <16 x i8>) nounwind
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