[llvm] r191193 - Partially revert r191192: Fix -Wunused-variable error when assertions are disabled and -Werror is in use.

[Daniel Sanders]

Author: dsanders
Date: Mon Sep 23 07:33:38 2013
New Revision: 191193

URL: http://llvm.org/viewvc/llvm-project?rev=191193&view=rev
Log:
Partially revert r191192: Fix -Wunused-variable error when assertions are disabled and -Werror is in use.

An unrelated change crept in because 'svn revert' isn't recursive by default.
The unrelated changes have been reverted.

Modified:
    llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=191193&r1=191192&r2=191193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Mon Sep 23 07:33:38 2013
@@ -162,17 +162,14 @@ addMSAIntType(MVT::SimpleValueType Ty, c
   setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
 
   setOperationAction(ISD::ADD, Ty, Legal);
-  setOperationAction(ISD::AND, Ty, Legal);
   setOperationAction(ISD::CTLZ, Ty, Legal);
   setOperationAction(ISD::MUL, Ty, Legal);
-  setOperationAction(ISD::OR, Ty, Legal);
   setOperationAction(ISD::SDIV, Ty, Legal);
   setOperationAction(ISD::SHL, Ty, Legal);
   setOperationAction(ISD::SRA, Ty, Legal);
   setOperationAction(ISD::SRL, Ty, Legal);
   setOperationAction(ISD::SUB, Ty, Legal);
   setOperationAction(ISD::UDIV, Ty, Legal);
-  setOperationAction(ISD::XOR, Ty, Legal);
 }
 
 // Enable MSA support for the given floating-point type and Register class.
@@ -898,8 +895,6 @@ SDValue MipsSETargetLowering::lowerINTRI
   case Intrinsic::mips_addv_w:
   case Intrinsic::mips_addv_d:
     return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
-  case Intrinsic::mips_and_v:
-    return lowerMSABinaryIntr(Op, DAG, ISD::AND);
   case Intrinsic::mips_bnz_b:
   case Intrinsic::mips_bnz_h:
   case Intrinsic::mips_bnz_w:
@@ -964,8 +959,6 @@ SDValue MipsSETargetLowering::lowerINTRI
   case Intrinsic::mips_nlzc_w:
   case Intrinsic::mips_nlzc_d:
     return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
-  case Intrinsic::mips_or_v:
-    return lowerMSABinaryIntr(Op, DAG, ISD::OR);
   case Intrinsic::mips_sll_b:
   case Intrinsic::mips_sll_h:
   case Intrinsic::mips_sll_w:
@@ -986,8 +979,6 @@ SDValue MipsSETargetLowering::lowerINTRI
   case Intrinsic::mips_subv_w:
   case Intrinsic::mips_subv_d:
     return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
-  case Intrinsic::mips_xor_v:
-    return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
   }
 }