[llvm] r191109 - [mips] MUL should clobber HI0 and LO0.

[Akira Hatanaka]

Author: ahatanak
Date: Fri Sep 20 16:22:28 2013
New Revision: 191109

URL: http://llvm.org/viewvc/llvm-project?rev=191109&view=rev
Log:
[mips] MUL should clobber HI0 and LO0.

I cannot think of a test case that reliably triggers this bug.



Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=191109&r1=191108&r2=191109&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep 20 16:22:28 2013
@@ -878,6 +878,7 @@ def ADDu  : MMRel, ArithLogicR<"addu", G
             ADD_FM<0, 0x21>;
 def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
             ADD_FM<0, 0x23>;
+let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
             ADD_FM<0x1c, 2>;
 def ADD   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;