[PATCH] Use the load-acquire/store-release instructions optimally in AArch32

[Artyom Skrobov]

Hello,

Owen doesn't seem to be available to review the change to
ARMISelLowering.cpp; would anyone else be so kind to step in?


-----Original Message-----
From: Artyom Skrobov 
Sent: 13 September 2013 09:20
To: 'llvm-commits at cs.uiuc.edu'
Cc: 'Owen Anderson'; 'Tim Northover'
Subject: RE: [PATCH] Use the load-acquire/store-release instructions
optimally in AArch32

Hello,

We're still waiting for feedback on the two outstanding issues:

1) whether all / some / none of the ATOMIC_xxx insts should explicitly have
mayLoad = 1, mayStore = 1

2) whether the change from getMemIntrinsicNode to getAtomic in
ReplaceATOMIC_OP_64 (in Tim's words, "extending the semantics of a
generic node") is a sensible approach.


-----Original Message-----
From: Artyom Skrobov 
Sent: 11 September 2013 17:55
To: 'Tim Northover'
Cc: Owen Anderson; llvm-commits at cs.uiuc.edu
Subject: RE: [PATCH] Use the load-acquire/store-release instructions
optimally in AArch32

Tim, do you suggest we add mayLoad/mayStore onto all ATOMIC_xxx insts, to be
on the safe side?
Following your explanation, I wonder why they didn't have mayLoad/mayStore
in the first place.


-----Original Message-----
From: Tim Northover [mailto:t.p.northover at gmail.com] 
Sent: 11 September 2013 14:22
To: Artyom Skrobov
Cc: Owen Anderson; llvm-commits at cs.uiuc.edu
Subject: Re: [PATCH] Use the load-acquire/store-release instructions
optimally in AArch32

Hi Artyom,

> I don't know why it was like this, but if I remove "mayLoad = 1,
>mayStore = 1" from the 64-bit ops, everything continues to work,
> so probably, they should not be there at all.

That doesn't necessarily follow. Those fields won't prevent anything
from compiling, but end up in ARMGenInstrInfo.inc and are checked by
various later MachineInstr passes. TableGen tries to infer them from
patterns attached to the instruction, but if there aren't any (and I
don't think Pats count (anotherFIXME)) the flags won't be set.

Anyway, I wouldn't expect mistakes to be noticed in any simple
examples. It'll strike when something decides it can CSE your atomic
operation or something equally nasty.

Cheers.

Tim.