[PATCH] Move memset value into register

[Nadav Rotem]

Hi, 

I am sorry for missing this patch the last time you sent it.  Do you have any performance numbers that show the profitability of this transformation ?  I also feel like SelectionDAG is not the right place to implement this kind of optimization. I think that introducing virtual registers would inhibit other optimizations on the DAG.  I also agree that this optimization can be generalized to any sequence of machine instructions that repeatedly use the same constant. 

I have a few comments on the patch itself.

You can commit the documentation of this method even without the change.

+/// \brief Lower the call to 'memset' intrinsic function into a series of store
+/// operations.
+///
+/// \param DAG Selection DAG where lowered code is placed.
+/// \param dl Link to corresponding IR location.

...

+/// The function tries to replace 'llvm.memset' intrinsic with several store
+/// operations and value calculation code. This is usually profitable for small
+/// memory size.
 static SDValue getMemsetStores(SelectionDAG &DAG, SDLoc dl,
                                SDValue Chain, SDValue Dst,
                                SDValue Src, uint64_t Size,


The code below is a little confusing.  Can you please add braces to the else clause, or at least separate the next statement with a line break ?


+  } else
+    LongestValueInReg = MemSetValue;
+  SDValue  RegInitialization = Chain;
+
   

Also here. Line break after the first "Value = “ line. I would also add braces around the last “Value = “ line.

+          TLI.isTruncateFree(LargestVT, VT)) {
+        if (ValueReg != 0)
+          Value = DAG.getCopyFromReg(RegInitialization, dl, ValueReg, LargestVT);
+        Value = DAG.getNode(ISD::TRUNCATE, dl, VT, Value);
+      }
       else
         Value = getMemsetValue(Src, VT, DAG, dl);
     }


Thanks,
Nadav


On Sep 16, 2013, at 2:55 PM, Chandler Carruth <chandlerc at google.com> wrote:

> I wonder whether this is the best approach.
> 
> Specifically, this is trading off register pressure for code size. I think it is probably the correct call in many cases, but perhaps not in all cases. Also, it has nothing to do with memset, and everything to do with any sequence of immediate operand movs.
> 
> I think this would be done somewhat better as an MI peephole that takes into account register pressure and how many mov instructions share the immediate to tradeoff the register pressure and potential instructions to materialize the constant into a register against the shrink of immediate operand movs.
> 
> But yes, Nadav or Andy would have more insights here...
> 
> 
> On Mon, Sep 16, 2013 at 10:00 AM, Serge Pavlov <sepavloff at gmail.com> wrote:
> Friendly ping.
> 
> 
> 2013/9/10 Serge Pavlov <sepavloff at gmail.com>
>   Cosmetical update to the patch
>   If block size is small, the size of largest move chunk may be smaller than the
>   natural register width and target may not have resisters of such width. Example
>   is 32-bit target that does not have 16-bit registers. Avoid allocation such
>   illegal registers.
> 
> Hi bkramer, nadav,
> 
> http://llvm-reviews.chandlerc.com/D1484
> 
> CHANGE SINCE LAST DIFF
>   http://llvm-reviews.chandlerc.com/D1484?vs=3692&id=4161#toc
> 
> Files:
>   include/llvm/Target/TargetLowering.h
>   lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>   lib/Target/X86/X86ISelLowering.cpp
>   lib/Target/X86/X86ISelLowering.h
>   test/CodeGen/X86/memset-sse-stack-realignment.ll
>   test/CodeGen/X86/memset.ll
>   test/CodeGen/X86/tlv-1.ll
> 
> 
> 
> -- 
> Thanks,
> --Serge
> 
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> 
> 

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