[llvm] r190780 - This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
Vladimir Medic
Vladimir.Medic at imgtec.com
Mon Sep 16 03:29:43 PDT 2013
Author: vmedic
Date: Mon Sep 16 05:29:42 2013
New Revision: 190780
URL: http://llvm.org/viewvc/llvm-project?rev=190780&view=rev
Log:
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/test/MC/Mips/mips-fpu-instructions.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=190780&r1=190779&r2=190780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Mon Sep 16 05:29:42 2013
@@ -125,6 +125,9 @@ class MipsAsmParser : public MCTargetAsm
MipsAsmParser::OperandMatchResultTy
parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+ MipsAsmParser::OperandMatchResultTy
+ parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+
bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
unsigned RegKind);
@@ -239,7 +242,8 @@ public:
Kind_FCCRegs,
Kind_ACC64DSP,
Kind_LO32DSP,
- Kind_HI32DSP
+ Kind_HI32DSP,
+ Kind_COP2
};
private:
@@ -457,6 +461,10 @@ public:
return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
}
+ bool isCOP2Asm() const {
+ return Kind == k_Register && Reg.Kind == Kind_COP2;
+ }
+
/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const {
return StartLoc;
@@ -1582,6 +1590,32 @@ MipsAsmParser::parseHI32DSP(SmallVectorI
Operands.push_back(Op);
Parser.Lex(); // Eat the register number.
+ return MatchOperand_Success;
+}
+
+MipsAsmParser::OperandMatchResultTy
+MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ // If the first token is not '$' we have an error.
+ if (Parser.getTok().isNot(AsmToken::Dollar))
+ return MatchOperand_NoMatch;
+
+ SMLoc S = Parser.getTok().getLoc();
+ Parser.Lex(); // Eat the '$'
+
+ const AsmToken &Tok = Parser.getTok(); // Get next token.
+
+ if (Tok.isNot(AsmToken::Integer))
+ return MatchOperand_NoMatch;
+
+ unsigned IntVal = Tok.getIntVal();
+
+ unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
+
+ MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
+ Op->setRegKind(MipsOperand::Kind_COP2);
+ Operands.push_back(Op);
+
+ Parser.Lex(); // Eat the register number.
return MatchOperand_Success;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=190780&r1=190779&r2=190780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Sep 16 05:29:42 2013
@@ -372,6 +372,14 @@ let Predicates = [NotFP64bit, HasStdEnc]
def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>;
}
+/// Cop2 Memory Instructions
+let Predicates = [HasStdEnc] in {
+ def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
+ def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
+ def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>;
+ def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>;
+}
+
// Indexed loads and stores.
let Predicates = [HasFPIdx, HasStdEnc] in {
def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>;
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=190780&r1=190779&r2=190780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Mon Sep 16 05:29:42 2013
@@ -201,6 +201,10 @@ let Namespace = "Mips" in {
foreach I = 0-7 in
def FCC#I : MipsReg<#I, "fcc"#I>;
+ // COP2 registers.
+ foreach I = 0-31 in
+ def COP2#I : MipsReg<#I, ""#I>;
+
// PC register
def PC : Register<"pc">;
@@ -368,6 +372,10 @@ def ACC64DSP : RegisterClass<"Mips", [un
def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
+// Coprocessor 2 registers.
+def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
+ Unallocatable;
+
// Register Operands.
class MipsAsmRegOperand : AsmOperandClass {
@@ -449,6 +457,11 @@ def HWRegsAsmOperand : MipsAsmRegOperand
let ParserMethod = "parseHWRegs";
}
+def COP2AsmOperand : MipsAsmRegOperand {
+ let Name = "COP2Asm";
+ let ParserMethod = "parseCOP2";
+}
+
def HWRegsOpnd : RegisterOperand<HWRegs> {
let ParserMatchClass = HWRegsAsmOperand;
}
@@ -484,3 +497,7 @@ def HI32DSPOpnd : RegisterOperand<HI32DS
def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
let ParserMatchClass = ACC64DSPAsmOperand;
}
+
+def COP2Opnd : RegisterOperand<COP2> {
+ let ParserMatchClass = COP2AsmOperand;
+}
Modified: llvm/trunk/test/MC/Mips/mips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-fpu-instructions.s?rev=190780&r1=190779&r2=190780&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-fpu-instructions.s Mon Sep 16 05:29:42 2013
@@ -169,6 +169,10 @@
# CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e]
# CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
# CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
+# CHECK: swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb]
+# CHECK: sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb]
+# CHECK: lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb]
+# CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]
cfc1 $a2,$0
ctc1 $10,$31
@@ -200,3 +204,7 @@
swxc1 $f26, $s2($s6)
mfhc1 $17, $f4
mthc1 $17, $f6
+ swc2 $4, 16($sp)
+ sdc2 $4, 16($sp)
+ lwc2 $11, 12($ra)
+ ldc2 $11, 12($ra)
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