[llvm] r190717 - Adds support for Atom Silvermont (SLM) - -march=slm

[Hal Finkel]

----- Original Message -----
> 
> 
> Just out of curiosity, when you have this:
> +  InstrItinData<IIC_SHD16_REG_IM, [InstrStage<2, [IEC_RSV0]>] >,
> 
> do you intend this to mean that the shift occupied the IEC_RSV0 unit,
> and nothing else can use it for 2 cycles? Or you do mean that the
> latency is 2 cycles, but you can still issue back-to-back
> independent shifts?
> 
>  -Hal
> 
> For the above itinerary, I am trying to represent that this
> instruction must use the IEC reservation station 0 and that it will
> take two cycles to execute. I would like to also be able to
> represent that the throughput of the instruction is 2 cycles, but I
> do not know how to do this.

Okay, that's what I thought. I think you want to say this:
  InstrItinData<IIC_SHD16_REG_IM, [InstrStage<1, [IEC_RSV0]>], [2, 1, 1] >,

The implementation is fully pipelined, right? Assuming that it is, you only need to track the first pipeline stage (because there are no hazards later). The numbers at the end say that the output operand will be ready in cycle 2 post-dispatch, and that the input operands are read in the first cycle.

I've cc'd Andy so that he can correct me if I'm wrong ;)

 -Hal

> 
> Preston
> 

-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory