[PATCH] AArch64: convert VPR64/VPR128 to RegisterOperands

[Tim Northover]

Hi Jiangning,

> I want to confirm with you that, the changes from VPR64 operand to VPR128 in
> patterns NeonI_3VDN_3Op and N2VShR_Narrow_Hi are because of the static
> checking of "let Constraints = "$src = $Rd";", true?

It was a dynamic failure, I believe, but that's definitely the
problem. CodeGen was deciding it needed to constrain the regclass to
be compatible with both $src and $Rd. Previously VPR128 and VPR64
contained the same set of registers (V0-V31) so this wasn't a problem.
Now the intersection of VPR128 (== FPR128) and VPR64 (== FPR64) is the
empty set and it will hit an assertion if the constrained vectors
aren't the same.

> Does the tblgen problem around InstAlias affect asm parser? I mean with this
> patch applied can end-user use "mov vD.8b, vN.8b" instruction in assembly
> code or not?

The user can still write that and it'll be interpreted correctly.
It'll just be printed back to them as "orr vD.8b, vN.8b, vN.8b".

Cheers.

Tim.