[llvm] r190618 - Implement asm support for a few PowerPC bookIII that are needed for assembling
Roman Divacky
rdivacky at freebsd.org
Thu Sep 12 10:50:54 PDT 2013
Author: rdivacky
Date: Thu Sep 12 12:50:54 2013
New Revision: 190618
URL: http://llvm.org/viewvc/llvm-project?rev=190618&view=rev
Log:
Implement asm support for a few PowerPC bookIII that are needed for assembling
FreeBSD kernel.
Added:
llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookIII.s
Modified:
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCSchedule.td
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=190618&r1=190617&r2=190618&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Thu Sep 12 12:50:54 2013
@@ -1360,6 +1360,8 @@ unsigned PPCAsmParser::validateTargetOpe
switch (Kind) {
case MCK_0: ImmVal = 0; break;
case MCK_1: ImmVal = 1; break;
+ case MCK_2: ImmVal = 2; break;
+ case MCK_3: ImmVal = 3; break;
default: return Match_InvalidOperand;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=190618&r1=190617&r2=190618&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Thu Sep 12 12:50:54 2013
@@ -398,6 +398,13 @@ class XForm_1a<bits<6> opcode, bits<10>
let RST = 0;
}
+class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let A = 0;
+ let B = 0;
+}
+
class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
@@ -438,6 +445,17 @@ class XForm_16<bits<6> opcode, bits<10>
let Inst{31} = 0;
}
+class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<5> RS;
+ bits<1> L;
+
+ let Inst{6-10} = RS;
+ let Inst{15} = L;
+ let Inst{21-30} = xo;
+}
+
class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
@@ -534,6 +552,21 @@ class XForm_43<bits<6> opcode, bits<10>
let Inst{31} = RC;
}
+class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let RST = 0;
+ let A = 0;
+ let B = 0;
+}
+
+class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+ let RST = 0;
+ let A = 0;
+}
+
// DCB_Form - Form X instruction, used for dcb* instructions.
class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=190618&r1=190617&r2=190618&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Thu Sep 12 12:50:54 2013
@@ -2319,6 +2319,35 @@ def EIEIO : XForm_24_eieio<31, 854, (out
def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
"wait $L", LdStLoad, []>;
+def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
+ "mtmsr $RS, $L", SprMTMSR>;
+
+def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
+ "mfmsr $RT", SprMFMSR, []>;
+
+def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
+ "mtmsrd $RS, $L", SprMTMSRD>;
+
+def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
+ "slbie $RB", SprSLBIE, []>;
+
+def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
+ "slbmte $RS, $RB", SprSLBMTE, []>;
+
+def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
+ "slbmfee $RT, $RB", SprSLBMFEE, []>;
+
+def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", SprSLBIA, []>;
+
+def TLBSYNC : XForm_0<31, 566, (outs), (ins),
+ "tlbsync", SprTLBSYNC, []>;
+
+def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
+ "tlbiel $RB", SprTLBIEL, []>;
+
+def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
+ "tlbie $RB,$RS", SprTLBIE, []>;
+
//===----------------------------------------------------------------------===//
// PowerPC Assembler Instruction Aliases
//
@@ -2387,6 +2416,46 @@ def : InstAlias<"sub. $rA, $rB, $rC", (S
def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
+def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
+def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
+
+def : InstAlias<"mfsprg $RT, 0", (MFSPR gprc:$RT, 272)>;
+def : InstAlias<"mfsprg $RT, 1", (MFSPR gprc:$RT, 273)>;
+def : InstAlias<"mfsprg $RT, 2", (MFSPR gprc:$RT, 274)>;
+def : InstAlias<"mfsprg $RT, 3", (MFSPR gprc:$RT, 275)>;
+
+def : InstAlias<"mfsprg0 $RT", (MFSPR gprc:$RT, 272)>;
+def : InstAlias<"mfsprg1 $RT", (MFSPR gprc:$RT, 273)>;
+def : InstAlias<"mfsprg2 $RT", (MFSPR gprc:$RT, 274)>;
+def : InstAlias<"mfsprg3 $RT", (MFSPR gprc:$RT, 275)>;
+
+def : InstAlias<"mtsprg 0, $RT", (MTSPR 272, gprc:$RT)>;
+def : InstAlias<"mtsprg 1, $RT", (MTSPR 273, gprc:$RT)>;
+def : InstAlias<"mtsprg 2, $RT", (MTSPR 274, gprc:$RT)>;
+def : InstAlias<"mtsprg 3, $RT", (MTSPR 275, gprc:$RT)>;
+
+def : InstAlias<"mtsprg0 $RT", (MTSPR 272, gprc:$RT)>;
+def : InstAlias<"mtsprg1 $RT", (MTSPR 273, gprc:$RT)>;
+def : InstAlias<"mtsprg2 $RT", (MTSPR 274, gprc:$RT)>;
+def : InstAlias<"mtsprg3 $RT", (MTSPR 275, gprc:$RT)>;
+
+def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
+
+def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
+def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
+
+def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
+
+def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
+def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
+
+def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
+def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
+def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
+def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
+
+def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
+
def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
(ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
Modified: llvm/trunk/lib/Target/PowerPC/PPCSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSchedule.td?rev=190618&r1=190617&r2=190618&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSchedule.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSchedule.td Thu Sep 12 12:50:54 2013
@@ -108,6 +108,14 @@ def VecPerm : InstrItinClass;
def VecFPRound : InstrItinClass;
def VecVSL : InstrItinClass;
def VecVSR : InstrItinClass;
+def SprMTMSRD : InstrItinClass;
+def SprSLIE : InstrItinClass;
+def SprSLBIE : InstrItinClass;
+def SprSLBMTE : InstrItinClass;
+def SprSLBMFEE : InstrItinClass;
+def SprSLBIA : InstrItinClass;
+def SprTLBIEL : InstrItinClass;
+def SprTLBIE : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
Added: llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookIII.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookIII.s?rev=190618&view=auto
==============================================================================
--- llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookIII.s (added)
+++ llvm/trunk/test/MC/PowerPC/ppc64-encoding-bookIII.s Thu Sep 12 12:50:54 2013
@@ -0,0 +1,107 @@
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
+
+# CHECK: mtmsr 4, 0 # encoding: [0x7c,0x80,0x01,0x24]
+ mtmsr %r4
+
+# CHECK: mtmsr 4, 1 # encoding: [0x7c,0x81,0x01,0x24]
+ mtmsr %r4, 1
+
+# CHECK: mfmsr 4 # encoding: [0x7c,0x80,0x00,0xa6]
+ mfmsr %r4
+
+# CHECK: mtmsrd 4, 0 # encoding: [0x7c,0x80,0x01,0x64]
+ mtmsrd %r4
+
+# CHECK: mtmsrd 4, 1 # encoding: [0x7c,0x81,0x01,0x64]
+ mtmsrd %r4, 1
+
+# CHECK: mfspr 4, 272 # encoding: [0x7c,0x90,0x42,0xa6]
+ mfsprg %r4, 0
+
+# CHECK: mfspr 4, 273 # encoding: [0x7c,0x91,0x42,0xa6]
+ mfsprg %r4, 1
+
+# CHECK: mfspr 4, 274 # encoding: [0x7c,0x92,0x42,0xa6]
+ mfsprg %r4, 2
+
+# CHECK: mfspr 4, 275 # encoding: [0x7c,0x93,0x42,0xa6]
+ mfsprg %r4, 3
+
+# CHECK: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6]
+ mtsprg 0, %r4
+
+# CHECK: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6]
+ mtsprg 1, %r4
+
+# CHECK: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6]
+ mtsprg 2, %r4
+
+# CHECK: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6]
+ mtsprg 3, %r4
+
+# CHECK: mtspr 272, 4 # encoding: [0x7c,0x90,0x43,0xa6]
+ mtsprg0 %r4
+
+# CHECK: mtspr 273, 4 # encoding: [0x7c,0x91,0x43,0xa6]
+ mtsprg1 %r4
+
+# CHECK: mtspr 274, 4 # encoding: [0x7c,0x92,0x43,0xa6]
+ mtsprg2 %r4
+
+# CHECK: mtspr 275, 4 # encoding: [0x7c,0x93,0x43,0xa6]
+ mtsprg3 %r4
+
+# CHECK: mtspr 280, 4 # encoding: [0x7c,0x98,0x43,0xa6]
+ mtasr %r4
+
+# CHECK: mfspr 4, 22 # encoding: [0x7c,0x96,0x02,0xa6]
+ mfdec %r4
+
+# CHECK: mtspr 22, 4 # encoding: [0x7c,0x96,0x03,0xa6]
+ mtdec %r4
+
+# CHECK: mfspr 4, 287 # encoding: [0x7c,0x9f,0x42,0xa6]
+ mfpvr %r4
+
+# CHECK: mfspr 4, 25 # encoding: [0x7c,0x99,0x02,0xa6]
+ mfsdr1 %r4
+
+# CHECK: mtspr 25, 4 # encoding: [0x7c,0x99,0x03,0xa6]
+ mtsdr1 %r4
+
+# CHECK: mfspr 4, 26 # encoding: [0x7c,0x9a,0x02,0xa6]
+ mfsrr0 %r4
+
+# CHECK: mtspr 26, 4 # encoding: [0x7c,0x9a,0x03,0xa6]
+ mtsrr0 %r4
+
+# CHECK: mfspr 4, 27 # encoding: [0x7c,0x9b,0x02,0xa6]
+ mfsrr1 %r4
+
+# CHECK: mtspr 27, 4 # encoding: [0x7c,0x9b,0x03,0xa6]
+ mtsrr1 %r4
+
+# CHECK: slbie 4 # encoding: [0x7c,0x00,0x23,0x64]
+ slbie %r4
+
+# CHECK: slbmte 4, 5 # encoding: [0x7c,0x80,0x2b,0x24]
+ slbmte %r4, %r5
+
+# CHECK: slbmfee 4, 5 # encoding: [0x7c,0x80,0x2f,0x26]
+ slbmfee %r4, %r5
+
+# CHECK: slbia # encoding: [0x7c,0x00,0x03,0xe4]
+ slbia
+
+# CHECK: tlbsync # encoding: [0x7c,0x00,0x04,0x6c]
+ tlbsync
+
+# CHECK: tlbiel 4 # encoding: [0x7c,0x00,0x22,0x24]
+ tlbiel %r4
+
+# CHECK: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64]
+ tlbie %r4, 0
+
+# CHECK: tlbie 4,0 # encoding: [0x7c,0x00,0x22,0x64]
+ tlbie %r4
+
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