[PATCH][AArch64] implement 3 aarch64 neon instrunctions (umov smov ins) in llvm

[Tim Northover]

Hi Kevin,

It's starting to look much nicer now.

> *Custom promote all 64 bit vector to 128 bit for EXTRACT_VECTOR_ELT and
> INSERT_VECTOR_ELT. ( the implementation maybe ugly, but currently I have no
> idea to get a better one. )

I've posted http://llvm-reviews.chandlerc.com/D1656, which implements
the RegisterOperand change and should allow you to use the expected
"sub_64" SUBREG operations as you tried in the beginning.

I'd appreciate you (and anyone else) taking a look.

I had another look through the whole patch, and have a few more
suggestions. There are one or two formatting issues with spaces at the
end of lines (particularly in .td files) and:

+                             neon_uimm4_bare> {
+                let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0},
0b1};
+                }

TableGen tends to use the normal LLVM 2-spaces for indentation style.

+void AArch64InstPrinter::printNeonUImm0OperandBare(const MCInst *MI,
+void AArch64InstPrinter::printNeonUImm8OperandBare(const MCInst *MI,

Are both of these functions needed?

Cheers.

Tim.