[PATCH][AArch64] implement 3 aarch64 neon instrunctions (umov smov ins) in llvm

[Tim Northover]

Hi Jiangning,

> I think you are meaning VPR128->FPR128->VPR64 is ugly.

Oh yes, I'd forgotten about that. In fact now that you've reminded me
it probably wouldn't work anyway.

> So do you mean we should completely remove register class VPR64 in
> AArch64RegisterInfo.td? And then we should define a new operand type derived
> from RegisterOperand to describe 64-bit vector register operand in patterns
> instead?

Pretty much. A new RegisterOperand for both VPR128 and VPR64, aliasing
them to FPR128 and FPR64 respectively.

I've attached a (completely broken, but compiles) patch showing what I
mean. AsmParser fought back so I couldn't get it anywhere near working
this morning. I'll see what I can do to improve it until it actually
works.

Cheers.

Tim.
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