[llvm] r190506 - [mips][msa] Separate the configuration of int/float vector types since they will diverge soon

[Daniel Sanders]

Author: dsanders
Date: Wed Sep 11 05:15:48 2013
New Revision: 190506

URL: http://llvm.org/viewvc/llvm-project?rev=190506&view=rev
Log:
[mips][msa] Separate the configuration of int/float vector types since they will diverge soon

No functional change


Modified:
    llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h

Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=190506&r1=190505&r2=190506&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Wed Sep 11 05:15:48 2013
@@ -83,13 +83,13 @@ MipsSETargetLowering::MipsSETargetLoweri
     setOperationAction(ISD::MUL, MVT::v2i16, Legal);
 
   if (Subtarget->hasMSA()) {
-    addMSAType(MVT::v16i8, &Mips::MSA128BRegClass);
-    addMSAType(MVT::v8i16, &Mips::MSA128HRegClass);
-    addMSAType(MVT::v4i32, &Mips::MSA128WRegClass);
-    addMSAType(MVT::v2i64, &Mips::MSA128DRegClass);
-    addMSAType(MVT::v8f16, &Mips::MSA128HRegClass);
-    addMSAType(MVT::v4f32, &Mips::MSA128WRegClass);
-    addMSAType(MVT::v2f64, &Mips::MSA128DRegClass);
+    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
+    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
+    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
+    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
+    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
+    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
+    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
   }
 
   if (!Subtarget->mipsSEUsesSoftFloat()) {
@@ -148,7 +148,21 @@ llvm::createMipsSETargetLowering(MipsTar
 }
 
 void MipsSETargetLowering::
-addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
+addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
+  addRegisterClass(Ty, RC);
+
+  // Expand all builtin opcodes.
+  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+    setOperationAction(Opc, Ty, Expand);
+
+  setOperationAction(ISD::BITCAST, Ty, Legal);
+  setOperationAction(ISD::LOAD, Ty, Legal);
+  setOperationAction(ISD::STORE, Ty, Legal);
+
+}
+
+void MipsSETargetLowering::
+addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
   addRegisterClass(Ty, RC);
 
   // Expand all builtin opcodes.

Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h?rev=190506&r1=190505&r2=190506&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.h Wed Sep 11 05:15:48 2013
@@ -22,7 +22,9 @@ namespace llvm {
   public:
     explicit MipsSETargetLowering(MipsTargetMachine &TM);
 
-    void addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
+    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
+    void addMSAFloatType(MVT::SimpleValueType Ty,
+                         const TargetRegisterClass *RC);
 
     virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;