[llvm] r190397 - Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.

[Vladimir Medic]

Author: vmedic
Date: Tue Sep 10 04:50:01 2013
New Revision: 190397

URL: http://llvm.org/viewvc/llvm-project?rev=190397&view=rev
Log:
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.

Modified:
    llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/trunk/test/MC/Mips/mips-fpu-instructions.s

Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=190397&r1=190396&r2=190397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Sep 10 04:50:01 2013
@@ -1404,6 +1404,10 @@ MipsAsmParser::parseRegs(SmallVectorImpl
       RegNum = matchFPURegisterName(RegName);
       if (RegKind == MipsOperand::Kind_AFGR64Regs)
         RegNum /= 2;
+      else if (RegKind == MipsOperand::Kind_FGRH32Regs
+               && !isFP64())
+        if (RegNum != -1 && RegNum %2 != 0)
+          Warning(S, "Float register should be even.");
       break;
     case MipsOperand::Kind_FCCRegs:
       RegNum = matchFCCRegisterName(RegName);

Modified: llvm/trunk/test/MC/Mips/mips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-fpu-instructions.s?rev=190397&r1=190396&r2=190397&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-fpu-instructions.s Tue Sep 10 04:50:01 2013
@@ -167,6 +167,8 @@
 # CHECK:  suxc1   $f4, $24($5)            # encoding: [0x0d,0x20,0xb8,0x4c]
 # CHECK:  lwxc1   $f20, $12($14)          # encoding: [0x00,0x05,0xcc,0x4d]
 # CHECK:  swxc1   $f26, $18($22)          # encoding: [0x08,0xd0,0xd2,0x4e]
+# CHECK:  mfhc1   $17, $f4                # encoding: [0x00,0x20,0x71,0x44]
+# CHECK:  mthc1   $17, $f6                # encoding: [0x00,0x30,0xf1,0x44]
 
    cfc1    $a2,$0
    ctc1    $10,$31
@@ -196,3 +198,5 @@
    suxc1   $f4, $t8($a1)
    lwxc1   $f20, $12($14)
    swxc1   $f26, $s2($s6)
+   mfhc1   $17, $f4
+   mthc1   $17, $f6