[llvm] r190180 - mi-sched: improve regpressure tracing.

[Andrew Trick]

Author: atrick
Date: Fri Sep  6 12:32:44 2013
New Revision: 190180

URL: http://llvm.org/viewvc/llvm-project?rev=190180&view=rev
Log:
mi-sched: improve regpressure tracing.

Modified:
    llvm/trunk/lib/CodeGen/MachineScheduler.cpp

Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=190180&r1=190179&r2=190180&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Fri Sep  6 12:32:44 2013
@@ -566,7 +566,8 @@ updateScheduledPressure(const std::vecto
       unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
       if (NewMaxPressure[i] > Limit ) {
         dbgs() << "  " << TRI->getRegPressureSetName(i) << ": "
-               << NewMaxPressure[i] << " > " << Limit << "\n";
+               << NewMaxPressure[i] << " > " << Limit << "(+ "
+               << BotRPTracker.getLiveThru()[i] << " livethru)\n";
       }
     });
 }
@@ -2454,6 +2455,10 @@ void ConvergingScheduler::tryCandidate(S
       }
     }
   }
+  DEBUG(if (TryCand.RPDelta.Excess.isValid())
+          dbgs() << "  SU(" << TryCand.SU->NodeNum << ") "
+                 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
+                 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
 
   // Initialize the candidate if needed.
   if (!Cand.isValid()) {
@@ -2614,7 +2619,7 @@ void ConvergingScheduler::traceCandidate
 }
 #endif
 
-/// Pick the best candidate from the top queue.
+/// Pick the best candidate from the queue.
 ///
 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
 /// DAG building. To adjust for the current scheduling location we need to