[llvm] r190154 - This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
Vladimir Medic
Vladimir.Medic at imgtec.com
Fri Sep 6 06:08:00 PDT 2013
Author: vmedic
Date: Fri Sep 6 08:08:00 2013
New Revision: 190154
URL: http://llvm.org/viewvc/llvm-project?rev=190154&view=rev
Log:
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
Added:
llvm/trunk/test/MC/Mips/micromips-multiply-instructions.s
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=190154&r1=190153&r2=190154&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Fri Sep 6 08:08:00 2013
@@ -129,4 +129,10 @@ let DecoderNamespace = "MicroMips", Pred
MFLO_FM_MM<0x035>;
def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>,
MFLO_FM_MM<0x075>;
+
+ /// Multiply Add/Sub Instructions
+ def MADD_MM : MMRel, MArithR<"madd", 1>, MULT_FM_MM<0x32c>;
+ def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>;
+ def MSUB_MM : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>;
+ def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=190154&r1=190153&r2=190154&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep 6 08:08:00 2013
@@ -413,7 +413,7 @@ class ArithLogicI<string opstr, Operand
// Arithmetic Multiply ADD/SUB
class MArithR<string opstr, bit isComm = 0> :
InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
- !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
+ !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
let Defs = [HI0, LO0];
let Uses = [HI0, LO0];
let isCommutable = isComm;
@@ -1044,10 +1044,10 @@ def NOP : PseudoSE<(outs), (ins), []>, P
def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
// MADD*/MSUB*
-def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
-def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
-def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
-def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
+def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
+def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
+def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
+def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips.txt?rev=190154&r1=190153&r2=190154&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips.txt Fri Sep 6 08:08:00 2013
@@ -171,3 +171,15 @@
# CHECK: mflo $6
0x00 0x06 0x1d 0x7c
+
+# CHECK: madd $4, $5
+0x00 0xa4 0xcb 0x3c
+
+# CHECK: maddu $4, $5
+0x00 0xa4 0xdb 0x3c
+
+# CHECK: msub $4, $5
+0x00 0xa4 0xeb 0x3c
+
+# CHECK: msubu $4, $5
+0x00 0xa4 0xfb 0x3c
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt?rev=190154&r1=190153&r2=190154&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips_le.txt Fri Sep 6 08:08:00 2013
@@ -171,3 +171,15 @@
# CHECK: mflo $6
0x06 0x00 0x7c 0x1d
+
+# CHECK: madd $4, $5
+0xa4 0x00 0x3c 0xcb
+
+# CHECK: maddu $4, $5
+0xa4 0x00 0x3c 0xdb
+
+# CHECK: msub $4, $5
+0xa4 0x00 0x3c 0xeb
+
+# CHECK: msubu $4, $5
+0xa4 0x00 0x3c 0xfb
Added: llvm/trunk/test/MC/Mips/micromips-multiply-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-multiply-instructions.s?rev=190154&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-multiply-instructions.s (added)
+++ llvm/trunk/test/MC/Mips/micromips-multiply-instructions.s Fri Sep 6 08:08:00 2013
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
+# RUN: | FileCheck -check-prefix=CHECK-EL %s
+# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
+# RUN: | FileCheck -check-prefix=CHECK-EB %s
+# Check that the assembler can handle the documented syntax
+# for Multiply Add/Sub instructions.
+#------------------------------------------------------------------------------
+# Multiply Add/Sub Instructions
+#------------------------------------------------------------------------------
+# Little endian
+#------------------------------------------------------------------------------
+# CHECK-EL: madd $4, $5 # encoding: [0xa4,0x00,0x3c,0xcb]
+# CHECK-EL: maddu $4, $5 # encoding: [0xa4,0x00,0x3c,0xdb]
+# CHECK-EL: msub $4, $5 # encoding: [0xa4,0x00,0x3c,0xeb]
+# CHECK-EL: msubu $4, $5 # encoding: [0xa4,0x00,0x3c,0xfb]
+#------------------------------------------------------------------------------
+# Big endian
+#------------------------------------------------------------------------------
+# CHECK-EB: madd $4, $5 # encoding: [0x00,0xa4,0xcb,0x3c]
+# CHECK-EB: maddu $4, $5 # encoding: [0x00,0xa4,0xdb,0x3c]
+# CHECK-EB: msub $4, $5 # encoding: [0x00,0xa4,0xeb,0x3c]
+# CHECK-EB: msubu $4, $5 # encoding: [0x00,0xa4,0xfb,0x3c]
+ madd $4, $5
+ maddu $4, $5
+ msub $4, $5
+ msubu $4, $5
More information about the llvm-commits
mailing list