[PATCH] Added a new register class for Thumb PC-rel loads

[Daniel Stewart]

Ah, yes, I see that. My apologies. When I changed the code for the
t2LEApcrelJT for the code that caused my issue, I saw the registers change.
Perhaps, however, it was simply a cascade effect of changing the ADR
registers. 

Just for kicks, the original code that caused me to look into this issue is
below. Note in this case, it's slightly different than the test case I
presented, in that the register used for the index is actually pushed and
then popped off the stack. 

In any event, I will approach this in a different manner. 

Daniel

0x00009d38:    fb049100    MLA      r1,r4,r0,r9
0x00009d3c:    1c62        ADDS     r2,r4,#1
0x00009d3e:    2808        CMP      r0,#8
0x00009d40:    f933e011    LDRSH    lr,[r3,r1,LSL #1]
0x00009d44:    f93b6b02    LDRSH    r6,[r11],#2
0x00009d48:    fb1e8806    SMLABB   r8,lr,r6,r8
0x00009d4c:    f0c08099    BCC.W    0x9e82 ; matrix_mul_matrix + 442
0x00009d50:    e055        B        0x9dfe ; matrix_mul_matrix + 310
0x00009d52:    f20f0226    ADR      r2,{pc}+0x28 ; 0x9d7a
0x00009d56:    eb02018a    ADD      r1,r2,r10,LSL #2
0x00009d5a:    f8ddb020    LDR      r11,[sp,#0x20]
0x00009d5e:    9106        STR      r1,[sp,#0x18]
0x00009d60:    2100        MOVS     r1,#0
0x00009d62:    f8dde018    LDR      lr,[sp,#0x18]
0x00009d66:    9109        STR      r1,[sp,#0x24]
0x00009d68:    f04f0800    MOV      r8,#0
0x00009d6c:    2700        MOVS     r7,#0
0x00009d6e:    2500        MOVS     r5,#0
0x00009d70:    2600        MOVS     r6,#0
0x00009d72:    2100        MOVS     r1,#0
0x00009d74:    2400        MOVS     r4,#0
0x00009d76:    2200        MOVS     r2,#0
0x00009d78:    46f7        MOV      pc,lr
0x00009d7a:    f000b840    B.W      0x9dfe ; matrix_mul_matrix + 310
0x00009d7e:    f000b83d    B.W      0x9dfc ; matrix_mul_matrix + 308
0x00009d82:    f000b831    B.W      0x9de8 ; matrix_mul_matrix + 288
0x00009d86:    f000b826    B.W      0x9dd6 ; matrix_mul_matrix + 270
0x00009d8a:    f000b81b    B.W      0x9dc4 ; matrix_mul_matrix + 252
0x00009d8e:    f000b810    B.W      0x9db2 ; matrix_mul_matrix + 234
0x00009d92:    f000b800    B.W      0x9d96 ; matrix_mul_matrix + 206
0x00009d96:    9c09        LDR      r4,[sp,#0x24]
0x00009d98:    f1c40a00    RSB      r10,r4,#0
0x00009d9c:    ea0a0500    AND      r5,r10,r0
0x00009da0:    eb050109    ADD      r1,r5,r9
0x00009da4:    f9332011    LDRSH    r2,[r3,r1,LSL #1]

-----Original Message-----
From: Tim Northover [mailto:t.p.northover at gmail.com] 
Sent: Thursday, September 05, 2013 11:40 AM
To: Tilmann Scheller
Cc: Daniel Stewart; Commits
Subject: Re: [PATCH] Added a new register class for Thumb PC-rel loads

> Correct, with your patch t2LEApcrelJT has the proper constraint to not 
> use LR for the destination register.
>
> My understanding is that the t2LEApcrelJT gets expanded to an ADR 
> instruction eventually. However, the MOV seems to be completely 
> independent of the t2LEApcrelJT, thus there's no way the constraint on 
> t2LEApcrelJT helps to constrain the source register of the MOV 
> (correct me if I'm wrong here).

It does look like it's BR_JT and friends that are the key instructions
needing to be constrained (referring to the lowering in ARMAsmPrinter.cpp to
see just which operands we don't want to be allocated in LR).

Cheers.

Tim.