[llvm] r190053 - Add AArch32 DCPS{1,2,3} and HLT instructions.
Richard Barton
richard.barton at arm.com
Thu Sep 5 07:14:20 PDT 2013
Author: rbarton
Date: Thu Sep 5 09:14:19 2013
New Revision: 190053
URL: http://llvm.org/viewvc/llvm-project?rev=190053&view=rev
Log:
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
Added:
llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s
llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s
llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
llvm/trunk/test/MC/Disassembler/ARM/thumb-v8.txt
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/diagnostics.s
llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=190053&r1=190052&r2=190053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 5 09:14:19 2013
@@ -1758,6 +1758,16 @@ def BKPT : AInoP<(outs), (ins imm0_65535
let Inst{7-4} = 0b0111;
}
+def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
+ "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
+ bits<16> val;
+ let Inst{3-0} = val{3-0};
+ let Inst{19-8} = val{15-4};
+ let Inst{27-20} = 0b00010000;
+ let Inst{31-28} = 0xe; // AL
+ let Inst{7-4} = 0b0111;
+}
+
// Change Processor State
// FIXME: We should use InstAlias to handle the optional operands.
class CPS<dag iops, string asm_ops>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=190053&r1=190052&r2=190053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Sep 5 09:14:19 2013
@@ -300,6 +300,13 @@ def tBKPT : T1I<(outs), (ins imm0_255:$v
let Inst{7-0} = val;
}
+def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
+ []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
+ let Inst{9-6} = 0b1010;
+ bits<6> val;
+ let Inst{5-0} = val;
+}
+
def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
[]>, T1Encoding<0b101101> {
bits<1> end;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=190053&r1=190052&r2=190053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Sep 5 09:14:19 2013
@@ -3645,6 +3645,20 @@ def t2SMC : T2I<(outs), (ins imm0_15:$op
let Inst{19-16} = opt;
}
+class T2DCPS<bits<2> opt, string opc>
+ : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
+ let Inst{31-27} = 0b11110;
+ let Inst{26-20} = 0b1111000;
+ let Inst{19-16} = 0b1111;
+ let Inst{15-12} = 0b1000;
+ let Inst{11-2} = 0b0000000000;
+ let Inst{1-0} = opt;
+}
+
+def t2DCPS1 : T2DCPS<0b01, "dcps1">;
+def t2DCPS2 : T2DCPS<0b10, "dcps2">;
+def t2DCPS3 : T2DCPS<0b11, "dcps3">;
+
class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: T2I<oops, iops, itin, opc, asm, pattern> {
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=190053&r1=190052&r2=190053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Sep 5 09:14:19 2013
@@ -4687,7 +4687,7 @@ StringRef ARMAsmParser::splitMnemonic(St
Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
- Mnemonic == "vaclt" || Mnemonic == "vacle" ||
+ Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
@@ -4793,7 +4793,7 @@ getMnemonicAcceptInfo(StringRef Mnemonic
if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
- Mnemonic == "trap" || Mnemonic == "setend" ||
+ Mnemonic == "trap" || Mnemonic == "hlt" ||
Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
@@ -5297,6 +5297,16 @@ static const MCInstrDesc &getInstDesc(un
return ARMInsts[Opcode];
}
+// Return true if instruction has the interesting property of being
+// allowed in IT blocks, but not being predicable.
+static bool instIsBreakpoint(const MCInst &Inst) {
+ return Inst.getOpcode() == ARM::tBKPT ||
+ Inst.getOpcode() == ARM::BKPT ||
+ Inst.getOpcode() == ARM::tHLT ||
+ Inst.getOpcode() == ARM::HLT;
+
+}
+
// FIXME: We would really like to be able to tablegen'erate this.
bool ARMAsmParser::
validateInstruction(MCInst &Inst,
@@ -5305,11 +5315,10 @@ validateInstruction(MCInst &Inst,
SMLoc Loc = Operands[0]->getStartLoc();
// Check the IT block state first.
- // NOTE: BKPT instruction has the interesting property of being
- // allowed in IT blocks, but not being predicable. It just always
- // executes.
- if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
- Inst.getOpcode() != ARM::BKPT) {
+ // NOTE: BKPT and HLT instructions have the interesting property of being
+ // allowed in IT blocks, but not being predicable. They just always
+ // execute.
+ if (inITBlock() && !instIsBreakpoint(Inst)) {
unsigned bit = 1;
if (ITState.FirstCond)
ITState.FirstCond = false;
Added: llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s?rev=190053&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s (added)
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions-v8.s Thu Sep 5 09:14:19 2013
@@ -0,0 +1,17 @@
+@ New ARMv8 A32 encodings
+
+@ RUN: llvm-mc -triple armv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
+@ RUN: not llvm-mc -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
+
+@ HLT
+ hlt #0
+ hlt #65535
+@ CHECK-V8: hlt #0 @ encoding: [0x70,0x00,0x00,0xe1]
+@ CHECK-V8: hlt #65535 @ encoding: [0x7f,0xff,0x0f,0xe1]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+
+@ AL condition code allowable
+ hltal #0
+@ CHECK-V8: hlt #0 @ encoding: [0x70,0x00,0x00,0xe1]
+@ CHECK-V7: error: instruction requires: armv8
Added: llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s?rev=190053&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s (added)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s Thu Sep 5 09:14:19 2013
@@ -0,0 +1,36 @@
+@ New ARMv8 T32 encodings
+
+@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
+@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
+
+@ HLT
+ hlt #0
+ hlt #63
+@ CHECK-V8: hlt #0 @ encoding: [0x80,0xba]
+@ CHECK-V8: hlt #63 @ encoding: [0xbf,0xba]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+
+@ In IT block
+ it pl
+ hlt #24
+
+@ CHECK-V8: it pl @ encoding: [0x58,0xbf]
+@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
+@ CHECK-V7: error: instruction requires: armv8
+
+@ Can accept AL condition code
+ hltal #24
+@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
+@ CHECK-V7: error: instruction requires: armv8
+
+@ DCPS{1,2,3}
+ dcps1
+ dcps2
+ dcps3
+@ CHECK-V8: dcps1 @ encoding: [0x8f,0xf7,0x01,0x80]
+@ CHECK-V8: dcps2 @ encoding: [0x8f,0xf7,0x02,0x80]
+@ CHECK-V8: dcps3 @ encoding: [0x8f,0xf7,0x03,0x80]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
Modified: llvm/trunk/test/MC/ARM/diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=190053&r1=190052&r2=190053&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/diagnostics.s Thu Sep 5 09:14:19 2013
@@ -1,5 +1,7 @@
@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
@ Check for various assembly diagnostic messages on invalid input.
@@ -93,6 +95,26 @@
@ CHECK-ERRORS: error: invalid operand for instruction
+ @ Out of range immediates for v8 HLT instruction.
+ hlt #65536
+ hlt #-1
+ at CHECK-ERRORS-V8: error: invalid operand for instruction
+ at CHECK-ERRORS-V8: hlt #65536
+ at CHECK-ERRORS-V8: ^
+ at CHECK-ERRORS-V8: error: invalid operand for instruction
+ at CHECK-ERRORS-V8: hlt #-1
+ at CHECK-ERRORS-V8: ^
+
+ @ Illegal condition code for v8 HLT instruction.
+ hlteq #2
+ hltlt #23
+ at CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
+ at CHECK-ERRORS-V8: hlteq #2
+ at CHECK-ERRORS-V8: ^
+ at CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
+ at CHECK-ERRORS-V8: hltlt #23
+ at CHECK-ERRORS-V8: ^
+
@ Out of range 4 and 3 bit immediates on CDP[2]
@ Out of range immediates for CDP/CDP2
Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=190053&r1=190052&r2=190053&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Thu Sep 5 09:14:19 2013
@@ -2,6 +2,8 @@
@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
+@ RUN: not llvm-mc -triple=thumbv8 < %s 2> %t
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
@ Check for various assembly diagnostic messages on invalid input.
@@ -38,6 +40,19 @@ error: invalid operand for instruction
bkpt #-1
^
+@ Out of range immediates for v8 HLT instruction.
+ hlt #64
+ hlt #-1
+ at CHECK-ERRORS: error: instruction requires: armv8 arm-mode
+ at CHECK-ERRORS: hlt #64
+ at CHECK-ERRORS: ^
+ at CHECK-ERRORS-V8: error: instruction requires: arm-mode
+ at CHECK-ERRORS-V8: hlt #64
+ at CHECK-ERRORS-V8: ^
+ at CHECK-ERRORS: error: invalid operand for instruction
+ at CHECK-ERRORS: hlt #-1
+ at CHECK-ERRORS: ^
+
@ Invalid writeback and register lists for LDM
ldm r2!, {r5, r8}
ldm r2, {r5, r7}
Added: llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt?rev=190053&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt Thu Sep 5 09:14:19 2013
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -disassemble -triple armv8 -show-encoding < %s | FileCheck %s
+
+# New v8 ARM instructions
+
+# HLT
+
+0x70 0x00 0x00 0xe1
+# CHECK: hlt #0
+
+0x7f 0xff 0x0f 0xe1
+# CHECK: hlt #65535
Added: llvm/trunk/test/MC/Disassembler/ARM/thumb-v8.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-v8.txt?rev=190053&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-v8.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-v8.txt Thu Sep 5 09:14:19 2013
@@ -0,0 +1,18 @@
+# RUN: llvm-mc -disassemble -triple thumbv8 -show-encoding < %s | FileCheck %s
+
+0x80 0xba
+# CHECK: hlt #0
+
+0xbf 0xba
+# CHECK: hlt #63
+
+# DCPS{1,2,3}
+
+0x8f 0xf7 0x01 0x80
+# CHECK: dcps1
+
+0x8f 0xf7 0x02 0x80
+# CHECK: dcps2
+
+0x8f 0xf7 0x03 0x80
+# CHECK: dcps3
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