[llvm] r189972 - ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.

[Jim Grosbach]

Author: grosbach
Date: Wed Sep  4 14:08:44 2013
New Revision: 189972

URL: http://llvm.org/viewvc/llvm-project?rev=189972&view=rev
Log:
ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.

These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093

Modified:
    llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp?rev=189972&r1=189971&r2=189972&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp Wed Sep  4 14:08:44 2013
@@ -657,6 +657,13 @@ bool A15SDOptimizer::runOnInstruction(Ma
         Modified = true;
         for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
                E = Uses.end(); I != E; ++I) {
+          // Make sure to constrain the register class of the new register to
+          // match what we're replacing. Otherwise we can optimize a DPR_VFP2
+          // reference into a plain DPR, and that will end poorly. NewReg is
+          // always virtual here, so there will always be a matching subclass
+          // to find.
+          MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
+
           DEBUG(dbgs() << "Replacing operand "
                        << **I << " with "
                        << PrintReg(NewReg) << "\n");