[llvm] r189841 - Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
Renato Golin
renato.golin at linaro.org
Wed Sep 4 06:16:59 PDT 2013
Hi Jim,
This patch broke our test-suite buildbot:
http://llvm.org/bugs/show_bug.cgi?id=17093
cheers,
--renato
PS: being redundant for the sake of llvm-commits history
On 3 September 2013 21:08, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Tue Sep 3 15:08:17 2013
> New Revision: 189841
>
> URL: http://llvm.org/viewvc/llvm-project?rev=189841&view=rev
> Log:
> Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""
>
> This reverts commit r189648.
>
> Fixes for the previously failing clang-side arm_neon_intrinsics test
> cases will be checked in separately.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> llvm/trunk/test/CodeGen/ARM/vmul.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=189841&r1=189840&r2=189841&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 3 15:08:17 2013
> @@ -4022,6 +4022,17 @@ def : Pat<(v4f32 (fmul (v4f32 QPR:$src1)
> (DSubReg_i32_reg imm:$lane))),
> (SubReg_i32_lane imm:$lane)))>;
>
> +
> +def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
> + (VMULslfd DPR:$Rn,
> + (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
> + (i32 0))>;
> +def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
> + (VMULslfq QPR:$Rn,
> + (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
> + (i32 0))>;
> +
> +
> // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
> defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D,
> IIC_VMULi32D,
> IIC_VMULi16Q, IIC_VMULi32Q,
>
> Modified: llvm/trunk/test/CodeGen/ARM/vmul.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=189841&r1=189840&r2=189841&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/vmul.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/vmul.ll Tue Sep 3 15:08:17 2013
> @@ -623,3 +623,21 @@ entry:
> store <4 x i32> %predphi290.v.i, <4 x i32>* undef, align 4
> ret void
> }
> +
> +define void @foo(<4 x float> * %a, <4 x float>* nocapture %dst, float*
> nocapture readonly %src) nounwind {
> +; Look for doing a normal scalar FP load rather than an to-all-lanes
> load.
> +; e.g., "ldr s0, [r2]" rathern than "vld1.32 {d18[], d19[]}, [r2:32]"
> +; Then check that the vector multiply has folded the splat to all lanes
> +; and used a vector * scalar instruction.
> +; CHECK: vldr {{s[0-9]+}}, [r2]
> +; CHECK: vmul.f32 q8, q8, d0[0]
> + %tmp = load float* %src, align 4
> + %tmp5 = load <4 x float>* %a, align 4
> + %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
> + %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
> + %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
> + %tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3
> + %tmp10 = fmul <4 x float> %tmp9, %tmp5
> + store <4 x float> %tmp10, <4 x float>* %dst, align 4
> + ret void
> +}
>
>
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