[llvm] r189742 - Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
NAKAMURA Takumi
geek4civic at gmail.com
Mon Sep 2 05:07:08 PDT 2013
It caused failures on AMD FX-8350, aka Piledriver. Please confirm my
tweaks in r189754.
...Takumi
2013/9/2 Craig Topper <craig.topper at gmail.com>:
> Author: ctopper
> Date: Mon Sep 2 02:53:17 2013
> New Revision: 189742
>
> URL: http://llvm.org/viewvc/llvm-project?rev=189742&view=rev
> Log:
> Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). Fixes PR17028.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/test/CodeGen/X86/bmi.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=189742&r1=189741&r2=189742&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 2 02:53:17 2013
> @@ -13693,6 +13693,7 @@ const char *X86TargetLowering::getTarget
> case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
> case X86ISD::BLSR: return "X86ISD::BLSR";
> case X86ISD::BZHI: return "X86ISD::BZHI";
> + case X86ISD::BEXTR: return "X86ISD::BEXTR";
> case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
> case X86ISD::PTEST: return "X86ISD::PTEST";
> case X86ISD::TESTP: return "X86ISD::TESTP";
> @@ -17503,6 +17504,7 @@ static SDValue PerformAndCombine(SDNode
> // BLSI is X & (-X)
> // BLSR is X & (X-1)
> // BZHI is X & ((1 << Y) - 1)
> + // BEXTR is ((X >> imm) & (2**size-1))
> if (VT == MVT::i32 || VT == MVT::i64) {
> SDValue N0 = N->getOperand(0);
> SDValue N1 = N->getOperand(1);
> @@ -17528,6 +17530,22 @@ static SDValue PerformAndCombine(SDNode
> if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
> isAllOnes(N1.getOperand(1)))
> return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
> +
> + // Check for BEXTR
> + if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) {
> + ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
> + ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
> + if (MaskNode && ShiftNode) {
> + uint64_t Mask = MaskNode->getZExtValue();
> + uint64_t Shift = ShiftNode->getZExtValue();
> + if (isMask_64(Mask)) {
> + uint64_t MaskSize = CountPopulation_64(Mask);
> + if (Shift + MaskSize <= VT.getSizeInBits())
> + return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
> + DAG.getConstant(Shift | (MaskSize << 8), VT));
> + }
> + }
> + }
> }
>
> if (Subtarget->hasBMI2()) {
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=189742&r1=189741&r2=189742&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Sep 2 02:53:17 2013
> @@ -296,6 +296,7 @@ namespace llvm {
> BLSMSK, // BLSMSK - Get mask up to lowest set bit
> BLSR, // BLSR - Reset lowest set bit
> BZHI, // BZHI - Zero high bits
> + BEXTR, // BEXTR - Bit field extract
>
> UMUL, // LOW, HI, FLAGS = umul LHS, RHS
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=189742&r1=189741&r2=189742&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep 2 02:53:17 2013
> @@ -253,6 +253,7 @@ def X86blsi : SDNode<"X86ISD::BLSI",
> def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
> def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
> def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
> +def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntShiftOp>;
>
> def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
>
> @@ -1869,6 +1870,15 @@ def : Pat<(X86bzhi (loadi64 addr:$src1),
> (BZHI64rm addr:$src1,
> (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
>
> +def : Pat<(X86bextr GR32:$src1, GR32:$src2),
> + (BEXTR32rr GR32:$src1, GR32:$src2)>;
> +def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
> + (BEXTR32rm addr:$src1, GR32:$src2)>;
> +def : Pat<(X86bextr GR64:$src1, GR64:$src2),
> + (BEXTR64rr GR64:$src1, GR64:$src2)>;
> +def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
> + (BEXTR64rm addr:$src1, GR64:$src2)>;
> +
> multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
> X86MemOperand x86memop, Intrinsic Int,
> PatFrag ld_frag> {
>
> Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=189742&r1=189741&r2=189742&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/bmi.ll Mon Sep 2 02:53:17 2013
> @@ -111,6 +111,23 @@ define i32 @bextr32_load(i32* %x, i32 %y
>
> declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
>
> +define i32 @bextr32b(i32 %x) nounwind uwtable readnone ssp {
> + %1 = lshr i32 %x, 4
> + %2 = and i32 %1, 4095
> + ret i32 %2
> +; CHECK-LABEL: bextr32b:
> +; CHECK: bextrl
> +}
> +
> +define i32 @bextr32b_load(i32* %x) nounwind uwtable readnone ssp {
> + %1 = load i32* %x
> + %2 = lshr i32 %1, 4
> + %3 = and i32 %2, 4095
> + ret i32 %3
> +; CHECK-LABEL: bextr32b_load:
> +; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
> +}
> +
> define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
> %tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
> ret i64 %tmp
> @@ -120,6 +137,14 @@ define i64 @bextr64(i64 %x, i64 %y) noun
>
> declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
>
> +define i64 @bextr64b(i64 %x) nounwind uwtable readnone ssp {
> + %1 = lshr i64 %x, 4
> + %2 = and i64 %1, 4095
> + ret i64 %2
> +; CHECK-LABEL: bextr64b:
> +; CHECK: bextrq
> +}
> +
> define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
> %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
> ret i32 %tmp
>
>
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