[llvm] r189490 - [ARMv8]
Joey Gouly
joey.gouly at arm.com
Wed Aug 28 09:39:20 PDT 2013
Author: joey
Date: Wed Aug 28 11:39:20 2013
New Revision: 189490
URL: http://llvm.org/viewvc/llvm-project?rev=189490&view=rev
Log:
[ARMv8]
Fix a few things in one swoop.
# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/test/MC/ARM/load-store-acquire-release-v8-thumb.s
llvm/trunk/test/MC/ARM/load-store-acquire-release-v8.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=189490&r1=189489&r2=189490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Aug 28 11:39:20 2013
@@ -2844,11 +2844,11 @@ multiclass AI3strT<bits<4> op, string op
defm STRHT : AI3strT<0b1011, "strht">;
-def STL : AIstrrel<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
+def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "stl", "\t$Rt, $addr", []>;
-def STLB : AIstrrel<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
+def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "stlb", "\t$Rt, $addr", []>;
-def STLH : AIstrrel<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
+def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "stlh", "\t$Rt, $addr", []>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=189490&r1=189489&r2=189490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 28 11:39:20 2013
@@ -1396,8 +1396,10 @@ def t2LDRHT : T2IldT<0, 0b01, "ldrht",
def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
-class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops, string opc, string asm, list<dag> pattern>
- : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, asm, "", pattern> {
+class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
+ string opc, string asm, list<dag> pattern>
+ : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
+ opc, asm, "", pattern>, Requires<[IsThumb, HasV8]> {
bits<4> Rt;
bits<4> addr;
@@ -1413,10 +1415,12 @@ class T2Ildacq<bits<4> bits23_20, bits<2
let Inst{15-12} = Rt;
}
-def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
-def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
-def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
-
+def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt),
+ (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>;
+def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
+ (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>;
+def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
+ (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>;
// Store
defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
@@ -1561,8 +1565,10 @@ def t2STRD_POST : T2Ii8s4post<0, 1, 0, (
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
"$addr.base = $wb", []>;
-class T2Istrrel<bits<2> bit54, dag oops, dag iops, string opc, string asm, list<dag> pattern>
- : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, asm, "", pattern> {
+class T2Istrrel<bits<2> bit54, dag oops, dag iops,
+ string opc, string asm, list<dag> pattern>
+ : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
+ asm, "", pattern>, Requires<[IsThumb, HasV8]> {
bits<4> Rt;
bits<4> addr;
@@ -1577,11 +1583,11 @@ class T2Istrrel<bits<2> bit54, dag oops,
let Inst{15-12} = Rt;
}
-def t2STL : T2Istrrel<0b10, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
+def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
"stl", "\t$Rt, $addr", []>;
-def t2STLB : T2Istrrel<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
+def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
"stlb", "\t$Rt, $addr", []>;
-def t2STLH : T2Istrrel<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
+def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
"stlh", "\t$Rt, $addr", []>;
// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
Modified: llvm/trunk/test/MC/ARM/load-store-acquire-release-v8-thumb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/load-store-acquire-release-v8-thumb.s?rev=189490&r1=189489&r2=189490&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/load-store-acquire-release-v8-thumb.s (original)
+++ llvm/trunk/test/MC/ARM/load-store-acquire-release-v8-thumb.s Wed Aug 28 11:39:20 2013
@@ -1,4 +1,5 @@
@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
+@ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
ldaexb r3, [r4]
ldaexh r2, [r5]
ldaex r1, [r7]
@@ -8,6 +9,10 @@
@ CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f]
@ CHECK: ldaex r1, [r7] @ encoding: [0xd7,0xe8,0xef,0x1f]
@ CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
stlexb r1, r3, [r4]
stlexh r4, r2, [r5]
@@ -17,6 +22,10 @@
@ CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f]
@ CHECK: stlex r2, r1, [r7] @ encoding: [0xc7,0xe8,0xe2,0x1f]
@ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
lda r5, [r6]
ldab r5, [r6]
@@ -24,6 +33,9 @@
@ CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f]
@ CHECK: ldab r5, [r6] @ encoding: [0xd6,0xe8,0x8f,0x5f]
@ CHECK: ldah r12, [r9] @ encoding: [0xd9,0xe8,0x9f,0xcf]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
stl r3, [r0]
stlb r2, [r1]
@@ -31,3 +43,6 @@
@ CHECK: stl r3, [r0] @ encoding: [0xc0,0xe8,0xaf,0x3f]
@ CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f]
@ CHECK: stlh r2, [r3] @ encoding: [0xc3,0xe8,0x9f,0x2f]
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: armv8
Modified: llvm/trunk/test/MC/ARM/load-store-acquire-release-v8.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/load-store-acquire-release-v8.s?rev=189490&r1=189489&r2=189490&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/load-store-acquire-release-v8.s (original)
+++ llvm/trunk/test/MC/ARM/load-store-acquire-release-v8.s Wed Aug 28 11:39:20 2013
@@ -1,4 +1,5 @@
@ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
+@ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
ldaexb r3, [r4]
ldaexh r2, [r5]
ldaex r1, [r7]
@@ -8,6 +9,10 @@
@ CHECK: ldaexh r2, [r5] @ encoding: [0x9f,0x2e,0xf5,0xe1]
@ CHECK: ldaex r1, [r7] @ encoding: [0x9f,0x1e,0x97,0xe1]
@ CHECK: ldaexd r6, r7, [r8] @ encoding: [0x9f,0x6e,0xb8,0xe1]
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
stlexb r1, r3, [r4]
stlexh r4, r2, [r5]
@@ -17,6 +22,10 @@
@ CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1]
@ CHECK: stlex r2, r1, [r7] @ encoding: [0x91,0x2e,0x87,0xe1]
@ CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1]
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
lda r5, [r6]
ldab r5, [r6]
@@ -24,6 +33,9 @@
@ CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1]
@ CHECK: ldab r5, [r6] @ encoding: [0x9f,0x5c,0xd6,0xe1]
@ CHECK: ldah r12, [r9] @ encoding: [0x9f,0xcc,0xf9,0xe1]
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
stl r3, [r0]
stlb r2, [r1]
@@ -31,3 +43,6 @@
@ CHECK: stl r3, [r0] @ encoding: [0x93,0xfc,0x80,0xe1]
@ CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1]
@ CHECK: stlh r2, [r3] @ encoding: [0x92,0xfc,0xe3,0xe1]
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: armv8
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