[llvm] r189465 - [mips][msa] Summarize tests
Daniel Sanders
daniel.sanders at imgtec.com
Wed Aug 28 03:02:29 PDT 2013
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Author: dsanders
Date: Wed Aug 28 05:02:29 2013
New Revision: 189465
URL: http://llvm.org/viewvc/llvm-project?rev=189465&view=rev
Log:
[mips][msa] Summarize tests
Adds a comment to the start of each test summarizing the area the test covers.
Modified:
llvm/trunk/test/CodeGen/Mips/msa/2r.ll
llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll
llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll
llvm/trunk/test/CodeGen/Mips/msa/bit.ll
llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll
llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll
llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll
llvm/trunk/test/CodeGen/Mips/msa/i8.ll
llvm/trunk/test/CodeGen/Mips/msa/spill.ll
llvm/trunk/test/CodeGen/Mips/msa/vec.ll
Modified: llvm/trunk/test/CodeGen/Mips/msa/2r.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2r.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2r.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2r.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the 2R instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2r_vector_scalar.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 2R instruction format and
+; convert scalars to vectors.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fill_b_ARG1 = global i32 23, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the 2RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_exup.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA floating point conversion intrinsics (e.g. float->double) that
+; are encoded with the 2RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_float_int.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA integer to floating point conversion intrinsics that are encoded
+; with the 2RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_fq.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA fixed-point to floating point conversion intrinsics that are
+; encoded with the 2RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_int_float.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,7 @@
+; Test the MSA floating point to integer intrinsics that are encoded with the
+; 2RF instruction format. This includes conversions but other instructions such
+; as fclass are also here.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/2rf_tq.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA floating-point to fixed-point conversion intrinsics that are
+; encoded with the 2RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-a.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'a'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-b.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'b'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-c.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'c'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-d.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'd'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-i.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'i'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-m.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'm'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-p.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'p'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-s.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 's'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r-v.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format.
+; There are lots of these so this covers those beginning with 'v'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_4r.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format and
+; use the result as a third operand.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_4r_widen.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,7 @@
+; Test the MSA intrinsics that are encoded with the 3R instruction format and
+; use the result as a third operand and results in wider elements than the
+; operands had.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3r_splat.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA splat intrinsics that are encoded with the 3R instruction
+; format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; use the result as a third operand.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_4rf_q.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; use the result as a third operand and perform fixed-point operations.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_exdo.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA floating-point conversion intrinsics that are encoded with the
+; 3RF instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_float_int.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; take an integer as an operand.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_int_float.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the 3RF instruction format and
+; produce an integer as a result.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_fceq_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/3rf_q.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
+; format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bit.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bit.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bit.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the BIT instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/bitcast.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,5 @@
+; Test the bitcast operation for big-endian and little-endian.
+
; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=LITENDIAN %s
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=BIGENDIAN %s
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_copy.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the ELM instruction format and
+; are element extraction operations.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_insv.ll Wed Aug 28 05:02:29 2013
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
-;
; Test the MSA element insertion intrinsics that are encoded with the ELM
; instruction format.
+; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+
@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_insert_b_ARG3 = global i32 27, align 16
@llvm_mips_insert_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/elm_shift_slide.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the ELM instruction format and
+; are either shifts or slides.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-a.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'a'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-b.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'b'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-c.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'c'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-m.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 'm'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i5-s.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test the MSA intrinsics that are encoded with the I5 instruction format.
+; There are lots of these so this covers those beginning with 's'
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i8.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/i8.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/i8.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,5 @@
+; Test the MSA intrinsics that are encoded with the I8 instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
Modified: llvm/trunk/test/CodeGen/Mips/msa/spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/spill.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/spill.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/spill.ll Wed Aug 28 05:02:29 2013
@@ -1,3 +1,6 @@
+; Test that the correct instruction is chosen for spill and reload by trying
+; to have 33 live MSA registers simultaneously
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind {
Modified: llvm/trunk/test/CodeGen/Mips/msa/vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/vec.ll?rev=189465&r1=189464&r2=189465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/vec.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/vec.ll Wed Aug 28 05:02:29 2013
@@ -1,7 +1,7 @@
+; Test the MSA intrinsics that are encoded with the VEC instruction format.
+
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
-;
-; Test the MSA intrinsics that are encoded with the VEC instruction format.
@llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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