[llvm] r189430 - [mips] Set isAllocatable and CoveredBySubRegs.

[Akira Hatanaka]

Author: ahatanak
Date: Tue Aug 27 19:34:17 2013
New Revision: 189430

URL: http://llvm.org/viewvc/llvm-project?rev=189430&view=rev
Log:
[mips] Set isAllocatable and CoveredBySubRegs.

Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=189430&r1=189429&r2=189430&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Tue Aug 27 19:34:17 2013
@@ -60,6 +60,7 @@ class AFPR<bits<16> Enc, string n, list<
 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
   : MipsRegWithSubRegs<Enc, n, subregs> {
   let SubRegIndices = [sub_lo, sub_hi];
+  let CoveredBySubRegs = 1;
 }
 
 // Mips 128-bit (aliased) MSA Registers
@@ -294,7 +295,8 @@ def CPUSPReg : RegisterClass<"Mips", [i3
 // * FGR32 - 32 32-bit registers (single float only mode)
 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
 
-def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>;
+def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
+             Unallocatable;
 
 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
   // Return Values and Arguments