[PATCH] [ms-inline asm] Support offsets after segment registers

[David Majnemer]

I couldn't add Chad to this code review via Phabricator but I'd like him to
take a look too.


On Thu, Aug 22, 2013 at 12:31 AM, David Majnemer
<david.majnemer at gmail.com>wrote:

> Hi craig.topper,
>
> MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'
>
> http://llvm-reviews.chandlerc.com/D1470
>
> Files:
>   lib/Target/X86/AsmParser/X86AsmParser.cpp
>   test/MC/X86/intel-syntax.s
>
> Index: lib/Target/X86/AsmParser/X86AsmParser.cpp
> ===================================================================
> --- lib/Target/X86/AsmParser/X86AsmParser.cpp
> +++ lib/Target/X86/AsmParser/X86AsmParser.cpp
> @@ -497,6 +497,8 @@
>    X86Operand *ParseIntelOffsetOfOperator();
>    X86Operand *ParseIntelDotOperator(const MCExpr *Disp, const MCExpr
> *&NewDisp);
>    X86Operand *ParseIntelOperator(unsigned OpKind);
> +  X86Operand *TryParseIntelSegmentOffset(unsigned SegReg, int64_t ImmDisp,
> +                                         SMLoc Start, SMLoc End, unsigned
> Size);
>    X86Operand *ParseIntelMemOperand(unsigned SegReg, int64_t ImmDisp,
>                                     SMLoc StartLoc);
>    X86Operand *ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
> @@ -1424,6 +1426,21 @@
>    return 0;
>  }
>
> +/// \brief Parse intel style segment offset.
> +X86Operand *X86AsmParser::TryParseIntelSegmentOffset(unsigned SegReg,
> +                                                     int64_t ImmDisp,
> +                                                     SMLoc Start, SMLoc
> End,
> +                                                     unsigned Size) {
> +  if (SegReg && (getLexer().is(AsmToken::Comma) ||
> +                 getLexer().is(AsmToken::EndOfStatement))) {
> +    // Handle things like INST SegReg : Imm, SRC
> +    //                and INST DST, SegReg : Imm
> +    const MCExpr *Disp = MCConstantExpr::Create(ImmDisp, getContext());
> +    return X86Operand::CreateMem(SegReg, Disp, /*BaseReg=*/0,
> /*IndexReg=*/0,
> +                                 /*Scale=*/1, Start, End, Size);
> +  }
> +  return 0;
> +}
>  /// ParseIntelMemOperand - Parse intel style memory operand.
>  X86Operand *X86AsmParser::ParseIntelMemOperand(unsigned SegReg,
>                                                 int64_t ImmDisp,
> @@ -1441,11 +1458,17 @@
>
>    // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
>    if (getLexer().is(AsmToken::Integer)) {
> +    int64_t ImmDisp = Tok.getIntVal();
> +    AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
> +
> +    if (X86Operand *SegmentOffsetOp = TryParseIntelSegmentOffset(
> +            SegReg, ImmDisp, Start, ImmDispToken.getEndLoc(), Size))
> +      return SegmentOffsetOp;
> +
>      if (isParsingInlineAsm())
>        InstInfo->AsmRewrites->push_back(AsmRewrite(AOK_ImmPrefix,
> -                                                  Tok.getLoc()));
> -    int64_t ImmDisp = Tok.getIntVal();
> -    Parser.Lex(); // Eat the integer.
> +                                                  ImmDispToken.getLoc()));
> +
>      if (getLexer().isNot(AsmToken::LBrac))
>        return ErrorOperand(Start, "Expected '[' token!");
>      return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
> @@ -1459,6 +1482,13 @@
>      if (getLexer().isNot(AsmToken::Colon))
>        return ErrorOperand(Start, "Expected ':' token!");
>      Parser.Lex(); // Eat :
> +    if (getLexer().is(AsmToken::Integer)) {
> +      int64_t ImmDisp = Tok.getIntVal();
> +      AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
> +      if (X86Operand *SegmentOffsetOp = TryParseIntelSegmentOffset(
> +              SegReg, ImmDisp, Start, ImmDispToken.getEndLoc(), Size))
> +        return SegmentOffsetOp;
> +    }
>      if (getLexer().isNot(AsmToken::LBrac))
>        return ErrorOperand(Start, "Expected '[' token!");
>      return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
> Index: test/MC/X86/intel-syntax.s
> ===================================================================
> --- test/MC/X86/intel-syntax.s
> +++ test/MC/X86/intel-syntax.s
> @@ -63,6 +63,10 @@
>      mov ECX, DWORD PTR [4*ECX + _fnan]
>  // CHECK: movq %fs:320, %rax
>      mov RAX, QWORD PTR FS:[320]
> +// CHECK: movq %fs:320, %rax
> +    mov RAX, QWORD PTR FS:320
> +// CHECK: movq %rax, %fs:320
> +    mov QWORD PTR FS:320, RAX
>  // CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
>      vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
>  // CHECK: movsd        -8, %xmm5
>
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