[PATCH] SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()
Tom Stellard
tom at stellard.net
Wed Aug 21 08:44:13 PDT 2013
Ping.
On Fri, Aug 16, 2013 at 09:27:09AM -0700, Tom Stellard wrote:
> From: Tom Stellard <thomas.stellard at amd.com>
>
> If we have a binary operation like ISD:ADD, we can set the result type
> equal to the result type of one of its operands rather than using
> TargetLowering::getPointerTy().
>
> Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary
> operation can be replaced with:
> DAG.getConstant(C, OtherOperand.getValueType());
> ---
> lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
> lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 44 +++----
> lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 11 +-
> lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp | 7 +-
> lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 +-
> lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 17 +--
> lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 6 +-
> test/CodeGen/R600/load.ll | 140 ++++++++++++++++++++++
> 8 files changed, 190 insertions(+), 43 deletions(-)
>
> diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> index ba23aac..bb092a3 100644
> --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> @@ -9865,7 +9865,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
> SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
> Cond, One, Zero);
> AddToWorkList(CstOffset.getNode());
> - CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
> + CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
> CstOffset);
> AddToWorkList(CPIdx.getNode());
> return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
> diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> index f52a0cd..a252796 100644
> --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> @@ -538,7 +538,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
> NewLoadedVT, LD->isVolatile(),
> LD->isNonTemporal(), Alignment);
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getConstant(IncrementSize, TLI.getPointerTy()));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
> LD->getPointerInfo().getWithOffset(IncrementSize),
> NewLoadedVT, LD->isVolatile(),
> @@ -548,7 +548,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
> NewLoadedVT, LD->isVolatile(),
> LD->isNonTemporal(), Alignment);
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getConstant(IncrementSize, TLI.getPointerTy()));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
> LD->getPointerInfo().getWithOffset(IncrementSize),
> NewLoadedVT, LD->isVolatile(),
> @@ -687,7 +687,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
> Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
> isNonTemporal, Alignment);
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(4));
> + DAG.getConstant(4, Ptr.getValueType()));
> Hi = DAG.getStore(Chain, dl, Hi, Ptr,
> ST->getPointerInfo().getWithOffset(4),
> isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
> @@ -793,7 +793,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
> // Store the remaining ExtraWidth bits.
> IncrementSize = RoundWidth / 8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
> DAG.getConstant(RoundWidth,
> TLI.getShiftAmountTy(Value.getValueType())));
> @@ -814,7 +814,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
> // Store the remaining ExtraWidth bits.
> IncrementSize = RoundWidth / 8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
> ST->getPointerInfo().getWithOffset(IncrementSize),
> ExtraVT, isVolatile, isNonTemporal,
> @@ -992,7 +992,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
> // Load the remaining ExtraWidth bits.
> IncrementSize = RoundWidth / 8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
> LD->getPointerInfo().getWithOffset(IncrementSize),
> ExtraVT, isVolatile, isNonTemporal,
> @@ -1021,7 +1021,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
> // Load the remaining ExtraWidth bits.
> IncrementSize = RoundWidth / 8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
> dl, Node->getValueType(0), Chain, Ptr,
> LD->getPointerInfo().getWithOffset(IncrementSize),
> @@ -1531,7 +1531,8 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
> unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
> unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
> LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
> - LoadPtr, DAG.getIntPtrConstant(ByteOffset));
> + LoadPtr,
> + DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
> // Load a legal integer containing the sign bit.
> SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
> false, false, false, 0);
> @@ -2232,11 +2233,11 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
> SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
>
> // word offset constant for Hi/Lo address computation
> - SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
> + SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
> // set up Hi and Lo (into buffer) address based on endian
> SDValue Hi = StackSlot;
> - SDValue Lo = DAG.getNode(ISD::ADD, dl,
> - TLI.getPointerTy(), StackSlot, WordOff);
> + SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
> + StackSlot, WordOff);
> if (TLI.isLittleEndian())
> std::swap(Hi, Lo);
>
> @@ -2395,7 +2396,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
>
> SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
> unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
> - CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
> + CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
> Alignment = std::min(Alignment, 4u);
> SDValue FudgeInReg;
> if (DestVT == MVT::f32)
> @@ -2947,20 +2948,20 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
> if (Align > TLI.getMinStackArgumentAlignment()) {
> assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
>
> - VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
> + VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
> DAG.getConstant(Align - 1,
> - TLI.getPointerTy()));
> + VAList.getValueType()));
>
> - VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
> + VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
> DAG.getConstant(-(int64_t)Align,
> - TLI.getPointerTy()));
> + VAList.getValueType()));
> }
>
> // Increment the pointer, VAList, to the next vaarg
> - Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
> + Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
> DAG.getConstant(TLI.getDataLayout()->
> getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
> - TLI.getPointerTy()));
> + VAList.getValueType()));
> // Store the incremented VAList to the legalized pointer
> Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
> MachinePointerInfo(V), false, false, 0);
> @@ -3572,9 +3573,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
> unsigned EntrySize =
> DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
>
> - Index = DAG.getNode(ISD::MUL, dl, PTy,
> - Index, DAG.getConstant(EntrySize, PTy));
> - SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
> + Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
> + Index, DAG.getConstant(EntrySize, Index.getValueType()));
> + SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
> + Index, Table);
>
> EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
> SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
> diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> index 643b1c9..5df36dd 100644
> --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> @@ -1844,7 +1844,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
> // Increment the pointer to the other half.
> unsigned IncrementSize = NVT.getSizeInBits()/8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
> N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
> isVolatile, isNonTemporal,
> @@ -1870,7 +1870,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
>
> // Increment the pointer to the other half.
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> // Load the rest of the low bits.
> Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
> N->getPointerInfo().getWithOffset(IncrementSize),
> @@ -2732,7 +2732,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
> // Increment the pointer to the other half.
> unsigned IncrementSize = NVT.getSizeInBits()/8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
> N->getPointerInfo().getWithOffset(IncrementSize),
> NEVT, isVolatile, isNonTemporal,
> @@ -2768,7 +2768,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
>
> // Increment the pointer to the other half.
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> // Store the lowest ExcessBits bits in the second half.
> Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
> N->getPointerInfo().getWithOffset(IncrementSize),
> @@ -2839,7 +2839,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
> SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
> Zero, Four);
> unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
> - FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
> + FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
> + FudgePtr, Offset);
> Alignment = std::min(Alignment, 4u);
>
> // Load the value out, extending it from f32 to the destination float type.
> diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
> index 96f6143..79a4070 100644
> --- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
> +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
> @@ -169,7 +169,8 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
> // Increment the pointer to the other half.
> unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
> StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize,
> + StackPtr.getValueType()));
>
> // Load the second half from the stack slot.
> Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr,
> @@ -262,7 +263,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
> // Increment the pointer to the other half.
> unsigned IncrementSize = NVT.getSizeInBits() / 8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
> LD->getPointerInfo().getWithOffset(IncrementSize),
> isVolatile, isNonTemporal, isInvariant,
> @@ -453,7 +454,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
> isVolatile, isNonTemporal, Alignment);
>
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
> Hi = DAG.getStore(Chain, dl, Hi, Ptr,
> St->getPointerInfo().getWithOffset(IncrementSize),
> diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> index 237a33a..56834d1 100644
> --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> @@ -433,7 +433,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
> RemainingBytes -= LoadBytes;
> Offset += LoadBytes;
> BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
> - DAG.getIntPtrConstant(LoadBytes));
> + DAG.getConstant(LoadBytes, BasePTR.getValueType()));
>
> LoadVals.push_back(ScalarLoad.getValue(0));
> LoadChains.push_back(ScalarLoad.getValue(1));
> @@ -501,7 +501,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
> LD->getAlignment());
>
> BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
> - DAG.getIntPtrConstant(Stride));
> + DAG.getConstant(Stride, BasePTR.getValueType()));
>
> Vals.push_back(ScalarLoad.getValue(0));
> LoadChains.push_back(ScalarLoad.getValue(1));
> @@ -560,7 +560,7 @@ SDValue VectorLegalizer::ExpandStore(SDValue Op) {
> isVolatile, isNonTemporal, Alignment);
>
> BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
> - DAG.getIntPtrConstant(Stride));
> + DAG.getConstant(Stride, BasePTR.getValueType()));
>
> Stores.push_back(Store);
> }
> diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> index 0406eb6..dca562a 100644
> --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> @@ -785,7 +785,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
> // Increment the pointer to the other part.
> unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
> StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, StackPtr.getValueType()));
>
> // Load the Hi part from the stack slot.
> Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
> @@ -827,7 +827,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
>
> unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
> Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
> - DAG.getIntPtrConstant(IncrementSize));
> + DAG.getConstant(IncrementSize, Ptr.getValueType()));
> Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
> LD->getPointerInfo().getWithOffset(IncrementSize),
> HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment);
> @@ -2580,7 +2580,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
> unsigned Increment = NewVTWidth / 8;
> Offset += Increment;
> BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
> - DAG.getIntPtrConstant(Increment));
> + DAG.getConstant(Increment, BasePtr.getValueType()));
>
> SDValue L;
> if (LdWidth < NewVTWidth) {
> @@ -2701,7 +2701,9 @@ DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
> unsigned i = 0, Offset = Increment;
> for (i=1; i < NumElts; ++i, Offset += Increment) {
> SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
> - BasePtr, DAG.getIntPtrConstant(Offset));
> + BasePtr,
> + DAG.getConstant(Offset,
> + BasePtr.getValueType()));
> Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
> LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
> isVolatile, isNonTemporal, Align);
> @@ -2758,7 +2760,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
> Offset += Increment;
> Idx += NumVTElts;
> BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
> - DAG.getIntPtrConstant(Increment));
> + DAG.getConstant(Increment, BasePtr.getValueType()));
> } while (StWidth != 0 && StWidth >= NewVTWidth);
> } else {
> // Cast the vector to the scalar type we can store
> @@ -2777,7 +2779,7 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
> StWidth -= NewVTWidth;
> Offset += Increment;
> BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
> - DAG.getIntPtrConstant(Increment));
> + DAG.getConstant(Increment, BasePtr.getValueType()));
> } while (StWidth != 0 && StWidth >= NewVTWidth);
> // Restore index back to be relative to the original widen element type
> Idx = Idx * NewVTWidth / ValEltWidth;
> @@ -2821,7 +2823,8 @@ DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
> unsigned Offset = Increment;
> for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
> SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
> - BasePtr, DAG.getIntPtrConstant(Offset));
> + BasePtr, DAG.getConstant(Offset,
> + BasePtr.getValueType()));
> SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
> DAG.getConstant(0, TLI.getVectorIdxTy()));
> StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
> diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> index 2a0c618..8e1cf54 100644
> --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> @@ -4709,14 +4709,14 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
> SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
> TLI->getPointerTy());
> SDValue Offset = DAG.getNode(ISD::ADD, sdl,
> - TLI->getPointerTy(),
> + CfaArg.getValueType(),
> DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
> - TLI->getPointerTy()),
> + CfaArg.getValueType()),
> CfaArg);
> SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
> TLI->getPointerTy(),
> DAG.getConstant(0, TLI->getPointerTy()));
> - setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI->getPointerTy(),
> + setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
> FA, Offset));
> return 0;
> }
> diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
> index 6cf1af7..c7fe611 100644
> --- a/test/CodeGen/R600/load.ll
> +++ b/test/CodeGen/R600/load.ll
> @@ -467,6 +467,76 @@ entry:
> ret void
> }
>
> +; R600-CHECK: @load_v2i8_local
> +; R600-CHECK: LDS_UBYTE_READ_RET
> +; R600-CHECK: LDS_UBYTE_READ_RET
> +; SI-CHECK: @load_v2i8_local
> +; SI-CHECK: DS_READ_U8
> +; SI-CHECK: DS_READ_U8
> +define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) {
> +entry:
> + %0 = load <2 x i8> addrspace(3)* %in
> + %1 = zext <2 x i8> %0 to <2 x i32>
> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +; R600-CHECK: @load_v2i8_sext_local
> +; R600-CHECK-DAG: LDS_UBYTE_READ_RET
> +; R600-CHECK-DAG: LDS_UBYTE_READ_RET
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; SI-CHECK: @load_v2i8_sext_local
> +; SI-CHECK: DS_READ_I8
> +; SI-CHECK: DS_READ_I8
> +define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) {
> +entry:
> + %0 = load <2 x i8> addrspace(3)* %in
> + %1 = sext <2 x i8> %0 to <2 x i32>
> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +; R600-CHECK: @load_v4i8_local
> +; R600-CHECK: LDS_UBYTE_READ_RET
> +; R600-CHECK: LDS_UBYTE_READ_RET
> +; R600-CHECK: LDS_UBYTE_READ_RET
> +; R600-CHECK: LDS_UBYTE_READ_RET
> +; SI-CHECK: @load_v4i8_local
> +; SI-CHECK: DS_READ_U8
> +; SI-CHECK: DS_READ_U8
> +; SI-CHECK: DS_READ_U8
> +; SI-CHECK: DS_READ_U8
> +define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) {
> +entry:
> + %0 = load <4 x i8> addrspace(3)* %in
> + %1 = zext <4 x i8> %0 to <4 x i32>
> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +; R600-CHECK: @load_v4i8_sext_local
> +; R600-CHECK-DAG: LDS_UBYTE_READ_RET
> +; R600-CHECK-DAG: LDS_UBYTE_READ_RET
> +; R600-CHECK-DAG: LDS_UBYTE_READ_RET
> +; R600-CHECK-DAG: LDS_UBYTE_READ_RET
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; SI-CHECK: @load_v4i8_sext_local
> +; SI-CHECK: DS_READ_I8
> +; SI-CHECK: DS_READ_I8
> +; SI-CHECK: DS_READ_I8
> +; SI-CHECK: DS_READ_I8
> +define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) {
> +entry:
> + %0 = load <4 x i8> addrspace(3)* %in
> + %1 = sext <4 x i8> %0 to <4 x i32>
> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> ; Load an i16 value from the local address space.
> ; R600-CHECK: @load_i16_local
> ; R600-CHECK: LDS_USHORT_READ_RET
> @@ -493,6 +563,76 @@ entry:
> ret void
> }
>
> +; R600-CHECK: @load_v2i16_local
> +; R600-CHECK: LDS_USHORT_READ_RET
> +; R600-CHECK: LDS_USHORT_READ_RET
> +; SI-CHECK: @load_v2i16_local
> +; SI-CHECK: DS_READ_U16
> +; SI-CHECK: DS_READ_U16
> +define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) {
> +entry:
> + %0 = load <2 x i16> addrspace(3)* %in
> + %1 = zext <2 x i16> %0 to <2 x i32>
> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +; R600-CHECK: @load_v2i16_sext_local
> +; R600-CHECK-DAG: LDS_USHORT_READ_RET
> +; R600-CHECK-DAG: LDS_USHORT_READ_RET
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; SI-CHECK: @load_v2i16_sext_local
> +; SI-CHECK: DS_READ_I16
> +; SI-CHECK: DS_READ_I16
> +define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) {
> +entry:
> + %0 = load <2 x i16> addrspace(3)* %in
> + %1 = sext <2 x i16> %0 to <2 x i32>
> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +; R600-CHECK: @load_v4i16_local
> +; R600-CHECK: LDS_USHORT_READ_RET
> +; R600-CHECK: LDS_USHORT_READ_RET
> +; R600-CHECK: LDS_USHORT_READ_RET
> +; R600-CHECK: LDS_USHORT_READ_RET
> +; SI-CHECK: @load_v4i16_local
> +; SI-CHECK: DS_READ_U16
> +; SI-CHECK: DS_READ_U16
> +; SI-CHECK: DS_READ_U16
> +; SI-CHECK: DS_READ_U16
> +define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) {
> +entry:
> + %0 = load <4 x i16> addrspace(3)* %in
> + %1 = zext <4 x i16> %0 to <4 x i32>
> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> +; R600-CHECK: @load_v4i16_sext_local
> +; R600-CHECK-DAG: LDS_USHORT_READ_RET
> +; R600-CHECK-DAG: LDS_USHORT_READ_RET
> +; R600-CHECK-DAG: LDS_USHORT_READ_RET
> +; R600-CHECK-DAG: LDS_USHORT_READ_RET
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; R600-CHECK-DAG: ASHR
> +; SI-CHECK: @load_v4i16_sext_local
> +; SI-CHECK: DS_READ_I16
> +; SI-CHECK: DS_READ_I16
> +; SI-CHECK: DS_READ_I16
> +; SI-CHECK: DS_READ_I16
> +define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) {
> +entry:
> + %0 = load <4 x i16> addrspace(3)* %in
> + %1 = sext <4 x i16> %0 to <4 x i32>
> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out
> + ret void
> +}
> +
> ; load an i32 value from the glocal address space.
> ; R600-CHECK: @load_i32_local
> ; R600-CHECK: LDS_READ_RET
> --
> 1.7.11.4
>
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