[llvm] r188896 - [mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.

[Daniel Sanders]

Author: dsanders
Date: Wed Aug 21 04:09:52 2013
New Revision: 188896

URL: http://llvm.org/viewvc/llvm-project?rev=188896&view=rev
Log:
[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.

I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.

This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.


Modified:
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=188896&r1=188895&r2=188896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Aug 21 04:09:52 2013
@@ -174,7 +174,7 @@ let Namespace = "Mips" in {
   /// Mips MSA registers
   /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
   foreach I = 0-31 in
-  def W#I : AFPR128<0, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
+  def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
             DwarfRegNum<[!add(I, 32)]>;
 
   // Hi/Lo registers