[llvm] r188551 - When initializing the PIC global base register on ARM/ELF add pc to fix the address.

[Benjamin Kramer]

Author: d0k
Date: Fri Aug 16 07:52:08 2013
New Revision: 188551

URL: http://llvm.org/viewvc/llvm-project?rev=188551&view=rev
Log:
When initializing the PIC global base register on ARM/ELF add pc to fix the address.

This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches
what GCC and SDag do for PIC but may not cover all of the many flavors of PIC
that exist.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=188551&r1=188550&r2=188551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Fri Aug 16 07:52:08 2013
@@ -130,6 +130,10 @@ namespace {
         MIB.addImm(0);
       AddDefaultPred(MIB);
 
+      // Fix the GOT address by adding pc.
+      BuildMI(FirstMBB, MBBI, DL, TII.get(ARM::tPICADD), GlobalBaseReg)
+          .addReg(GlobalBaseReg).addImm(ARMPCLabelIndex);
+
       return true;
     }
 

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll?rev=188551&r1=188550&r2=188551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-pic.ll Fri Aug 16 07:52:08 2013
@@ -25,6 +25,8 @@ entry:
 ; ARMv7: add  [[reg2]], pc, [[reg2]]
 ; ARMv7-ELF: LoadGV
 ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
+; ARMv7-ELF: .LPC
+; ARMv7-ELF-NEXT: add r[[reg2]], pc
 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
   %tmp = load i32* @g
@@ -54,6 +56,8 @@ entry:
 ; ARMv7: ldr  r[[reg5]], [r[[reg5]]]
 ; ARMv7-ELF: LoadIndirectSymbol
 ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
+; ARMv7-ELF: .LPC
+; ARMv7-ELF-NEXT: add r[[reg5]], pc
 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
   %tmp = load i32* @i