[llvm] r188523 - Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"
Tom Stellard
thomas.stellard at amd.com
Thu Aug 15 18:18:43 PDT 2013
Author: tstellar
Date: Thu Aug 15 20:18:43 2013
New Revision: 188523
URL: http://llvm.org/viewvc/llvm-project?rev=188523&view=rev
Log:
Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"
This reverts commit a6a39ced095c2f453624ce62c4aead25db41a18f.
This is the wrong version of this fix.
Modified:
llvm/trunk/lib/Target/R600/SIInsertWaits.cpp
llvm/trunk/lib/Target/R600/SIInstrInfo.td
llvm/trunk/lib/Target/R600/SIInstructions.td
llvm/trunk/test/CodeGen/R600/local-memory.ll
Modified: llvm/trunk/lib/Target/R600/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInsertWaits.cpp?rev=188523&r1=188522&r2=188523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInsertWaits.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInsertWaits.cpp Thu Aug 15 20:18:43 2013
@@ -134,7 +134,9 @@ Counters SIInsertWaits::getHwCounts(Mach
// LGKM may uses larger values
if (TSFlags & SIInstrFlags::LGKM_CNT) {
- const MachineOperand &Op = MI.getOperand(0);
+ MachineOperand &Op = MI.getOperand(0);
+ if (!Op.isReg())
+ Op = MI.getOperand(1);
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=188523&r1=188522&r2=188523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Thu Aug 15 20:18:43 2013
@@ -342,8 +342,8 @@ class VOP3_64 <bits<9> op, string opName
class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs regClass:$vdst),
- (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
- i8imm:$offset0, i8imm:$offset1, i1imm:$gds),
+ (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
+ i8imm:$offset0, i8imm:$offset1),
asm#" $vdst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
[]> {
let mayLoad = 1;
@@ -353,8 +353,8 @@ class DS_Load_Helper <bits<8> op, string
class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
op,
(outs),
- (ins VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
- i8imm:$offset0, i8imm:$offset1, i1imm:$gds),
+ (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
+ i8imm:$offset0, i8imm:$offset1),
asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
[]> {
let mayStore = 1;
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=188523&r1=188522&r2=188523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Thu Aug 15 20:18:43 2013
@@ -1745,13 +1745,13 @@ def : Pat <
def : Pat <
(local_load i64:$src0),
- (i32 (DS_READ_B32 (EXTRACT_SUBREG $src0, sub0),
- (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0, 0))
+ (i32 (DS_READ_B32 0, (EXTRACT_SUBREG $src0, sub0),
+ (EXTRACT_SUBREG $src0, sub0), (EXTRACT_SUBREG $src0, sub0), 0, 0))
>;
def : Pat <
(local_store i32:$src1, i64:$src0),
- (DS_WRITE_B32 (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0, 0)
+ (DS_WRITE_B32 0, (EXTRACT_SUBREG $src0, sub0), $src1, $src1, 0, 0)
>;
/********** ================== **********/
Modified: llvm/trunk/test/CodeGen/R600/local-memory.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/local-memory.ll?rev=188523&r1=188522&r2=188523&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/local-memory.ll (original)
+++ llvm/trunk/test/CodeGen/R600/local-memory.ll Thu Aug 15 20:18:43 2013
@@ -13,7 +13,7 @@
; SI-CHECK-NEXT: .long 32768
; EG-CHECK: LDS_WRITE
-; SI-CHECK: DS_WRITE_B32 0
+; SI-CHECK: DS_WRITE_B32
; GROUP_BARRIER must be the last instruction in a clause
; EG-CHECK: GROUP_BARRIER
@@ -21,7 +21,7 @@
; SI-CHECK: S_BARRIER
; EG-CHECK: LDS_READ_RET
-; SI-CHECK: DS_READ_B32 VGPR{{[0-9]}}, 0
+; SI-CHECK: DS_READ_B32
define void @local_memory(i32 addrspace(1)* %out) {
entry:
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