[PATCH] let tablegen compute maximum lanemask for a regs/regclasses

[Matthias Braun]

MatzeB added you to the CC list for the revision "let tablegen compute maximum lanemask for a regs/regclasses".

Let tablegen compute the combination of subregister lanemasks for all
subregisters in a register/register class. This is preparation for further
work subregister allocation

http://llvm-reviews.chandlerc.com/D1392

Files:
  include/llvm/Target/TargetRegisterInfo.h
  utils/TableGen/CodeGenRegisters.cpp
  utils/TableGen/CodeGenRegisters.h
  utils/TableGen/RegisterInfoEmitter.cpp

Index: include/llvm/Target/TargetRegisterInfo.h
===================================================================
--- include/llvm/Target/TargetRegisterInfo.h
+++ include/llvm/Target/TargetRegisterInfo.h
@@ -45,6 +45,7 @@
   const vt_iterator VTs;
   const uint32_t *SubClassMask;
   const uint16_t *SuperRegIndices;
+  const unsigned LaneMask;
   const sc_iterator SuperClasses;
   ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
 
@@ -194,13 +195,21 @@
   ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
     return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
   }
+
+  /// return the combination of all lanemasks of register in this class.
+  /// The lanemasks of the registers are again the combination of all lanemasks
+  /// of their subregisters.
+  unsigned getLaneMask() const {
+    return LaneMask;
+  }
 };
 
 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
 /// registers. These are used by codegen, not by MC.
 struct TargetRegisterInfoDesc {
   unsigned CostPerUse;          // Extra cost of instructions using register.
   bool inAllocatableClass;      // Register belongs to an allocatable regclass.
+  unsigned LaneMask;            // combination of all subregister lane masks
 };
 
 /// Each TargetRegisterClass has a per register weight, and weight
@@ -364,6 +373,13 @@
     return SubRegIndexLaneMasks[SubIdx];
   }
 
+  /// Returns the combination of all lanemasks of subregisters of this register.
+  /// This means that if A is a subregister of B, then:
+  ///    getSubRegIndexLaneMask(A) & ~getLaneMak(B) == 0
+  unsigned getLaneMask(unsigned RegNo) const {
+    return InfoDesc[RegNo].LaneMask;
+  }
+
   /// The lane masks returned by getSubRegIndexLaneMask() above can only be
   /// used to determine if sub-registers overlap - they can't be used to
   /// determine if a set of sub-registers completely cover another
Index: utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- utils/TableGen/CodeGenRegisters.cpp
+++ utils/TableGen/CodeGenRegisters.cpp
@@ -1173,7 +1173,7 @@
 //
 // Conservatively share a lane mask bit if two sub-register indices overlap in
 // some registers, but not in others. That shouldn't happen a lot.
-void CodeGenRegBank::computeSubRegIndexLaneMasks() {
+void CodeGenRegBank::computeSubRegLaneMasks() {
   // First assign individual bits to all the leaf indices.
   unsigned Bit = 0;
   // Determine mask of lanes that cover their registers.
@@ -1211,6 +1211,30 @@
     if (!SubRegIndices[i]->AllSuperRegsCovered)
       CoveringLanes &= ~Mask;
   }
+
+  // compute lanemask combinations for registers
+  for (size_t r = 0, re = Registers.size(); r != re; ++r) {
+    CodeGenRegister *Register = Registers[r];
+    const CodeGenRegister::SubRegMap &SubRegs = Register->getSubRegs();
+    unsigned LaneMask = 0;
+    for (CodeGenRegister::SubRegMap::const_iterator S = SubRegs.begin(),
+         SE = SubRegs.end(); S != SE; ++S) {
+      LaneMask |= S->first->LaneMask;
+    }
+    Register->LaneMask = LaneMask;
+  }
+
+  // compute lanemask combinations for register classes
+  for (size_t c = 0, ce = RegClasses.size(); c != ce; ++c) {
+    CodeGenRegisterClass *RegClass = RegClasses[c];
+    const CodeGenRegister::Set &Registers = RegClass->getMembers();
+    unsigned LaneMask = 0;
+    for (CodeGenRegister::Set::iterator R = Registers.begin(),
+         RE = Registers.end(); R != RE; ++R) {
+      LaneMask |= (*R)->LaneMask;
+    }
+    RegClass->LaneMask = LaneMask;
+  }
 }
 
 namespace {
@@ -1716,7 +1740,7 @@
 
 void CodeGenRegBank::computeDerivedInfo() {
   computeComposites();
-  computeSubRegIndexLaneMasks();
+  computeSubRegLaneMasks();
 
   // Compute a weight for each register unit created during getSubRegs.
   // This may create adopted register units (with unit # >= NumNativeRegUnits).
Index: utils/TableGen/CodeGenRegisters.h
===================================================================
--- utils/TableGen/CodeGenRegisters.h
+++ utils/TableGen/CodeGenRegisters.h
@@ -111,6 +111,8 @@
     Record *TheDef;
     unsigned EnumValue;
     unsigned CostPerUse;
+    /// combination of the lanemasks of all subregisters
+    unsigned LaneMask;
     bool CoveredBySubRegs;
 
     // Map SubRegIndex -> Register.
@@ -279,6 +281,8 @@
     int CopyCost;
     bool Allocatable;
     std::string AltOrderSelect;
+    /// combination of the lanemasks of all subregisters
+    unsigned LaneMask;
 
     // Return the Record that defined this class, or NULL if the class was
     // created by TableGen.
@@ -519,7 +523,7 @@
     void computeComposites();
 
     // Compute a lane mask for each sub-register index.
-    void computeSubRegIndexLaneMasks();
+    void computeSubRegLaneMasks();
 
   public:
     CodeGenRegBank(RecordKeeper&);
Index: utils/TableGen/RegisterInfoEmitter.cpp
===================================================================
--- utils/TableGen/RegisterInfoEmitter.cpp
+++ utils/TableGen/RegisterInfoEmitter.cpp
@@ -1182,7 +1182,8 @@
          << "RegClassID],\n    "
          << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n    "
          << RC.getName() << "SubClassMask,\n    SuperRegIdxSeqs + "
-         << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n    ";
+         << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n    "
+         << format("0x%08x,\n    ", RC.LaneMask);
       if (RC.getSuperClasses().empty())
         OS << "NullRegClasses,\n    ";
       else
@@ -1209,14 +1210,15 @@
   const std::string &TargetName = Target.getName();
   OS << "\nstatic const TargetRegisterInfoDesc "
      << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
-  OS << "  { 0, 0 },\n";
+  OS << "  { 0, 0, 0x00000000 },\n";
 
   const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     const CodeGenRegister &Reg = *Regs[i];
     OS << "  { ";
     OS << Reg.CostPerUse << ", "
-       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
+       << int(AllocatableRegs.count(Reg.TheDef)) << ", "
+       << format("0x%08x },\n", Reg.LaneMask);
   }
   OS << "};\n";      // End of register descriptors...
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