[llvm] r188162 - [SystemZ] Add a definition of the CLC instruction
Richard Sandiford
rsandifo at linux.vnet.ibm.com
Mon Aug 12 03:17:34 PDT 2013
Author: rsandifo
Date: Mon Aug 12 05:17:33 2013
New Revision: 188162
URL: http://llvm.org/viewvc/llvm-project?rev=188162&view=rev
Log:
[SystemZ] Add a definition of the CLC instruction
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Mon Aug 12 05:17:33 2013
@@ -1701,6 +1701,7 @@ const char *SystemZTargetLowering::getTa
OPCODE(UDIVREM32);
OPCODE(UDIVREM64);
OPCODE(MVC);
+ OPCODE(CLC);
OPCODE(ATOMIC_SWAPW);
OPCODE(ATOMIC_LOADW_ADD);
OPCODE(ATOMIC_LOADW_SUB);
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h Mon Aug 12 05:17:33 2013
@@ -80,6 +80,10 @@ namespace SystemZISD {
// MachineMemOperands rather than one.
MVC,
+ // Use CLC to compare two blocks of memory, with the same comments
+ // as for MVC.
+ CLC,
+
// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
// ATOMIC_LOAD_<op>.
//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Mon Aug 12 05:17:33 2013
@@ -1386,3 +1386,22 @@ class AtomicLoadWBinaryReg<SDPatternOper
: AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
: AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
+
+// Define an instruction that operates on two fixed-length blocks of memory.
+// The real instruction uses a bdladdr12onlylen8 for the first operand and a
+// bdaddr12only for the second, with the length of the second operand being
+// implicitly the same as the first. This arrangement matches the underlying
+// assembly syntax. However, for instruction selection it's easier to have
+// two normal bdaddr12onlys and a separate length operand, so define a pseudo
+// instruction for that too.
+multiclass MemorySS<string mnemonic, bits<8> opcode,
+ SDPatternOperator operator> {
+ def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
+ bdaddr12only:$BD2),
+ mnemonic##"\t$BDL1, $BD2", []>;
+ let usesCustomInserter = 1 in
+ def Wrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
+ imm32len8:$length),
+ [(operator bdaddr12only:$dest, bdaddr12only:$src,
+ imm32len8:$length)]>;
+}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Mon Aug 12 05:17:33 2013
@@ -334,15 +334,7 @@ def MVGHI : StoreSIL<"mvghi", 0xE548, st
// Memory-to-memory moves.
let mayLoad = 1, mayStore = 1 in
- def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1,
- bdaddr12only:$BD2),
- "mvc\t$BDL1, $BD2", []>;
-
-let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in
- def MVCWrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
- imm32len8:$length),
- [(z_mvc bdaddr12only:$dest, bdaddr12only:$src,
- imm32len8:$length)]>;
+ defm MVC : MemorySS<"mvc", 0xD2, z_mvc>;
defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32,
MVCWrapper, 1>;
@@ -1000,6 +992,10 @@ let Defs = [CC], CCValues = 0xE, IsLogic
}
defm : ZXB<z_ucmp, GR64, CLGFR>;
+// Memory-to-memory comparison.
+let mayLoad = 1, Defs = [CC] in
+ defm CLC : MemorySS<"clc", 0xD5, z_clc>;
+
//===----------------------------------------------------------------------===//
// Atomic operations
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperators.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperators.td?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZOperators.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperators.td Mon Aug 12 05:17:33 2013
@@ -54,7 +54,7 @@ def SDT_ZAtomicCmpSwapW : SDTypeProf
SDTCisVT<4, i32>,
SDTCisVT<5, i32>,
SDTCisVT<6, i32>]>;
-def SDT_ZCopy : SDTypeProfile<0, 3,
+def SDT_ZMemMemLength : SDTypeProfile<0, 3,
[SDTCisPtrTy<0>,
SDTCisPtrTy<1>,
SDTCisVT<2, i32>]>;
@@ -109,8 +109,10 @@ def z_atomic_loadw_umin : AtomicWOp<"ATO
def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
-def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZCopy,
+def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
+def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
+ [SDNPHasChain, SDNPMayLoad]>;
//===----------------------------------------------------------------------===//
// Pattern fragments
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Mon Aug 12 05:17:33 2013
@@ -1333,6 +1333,42 @@
# CHECK: chy %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x79
+# CHECK: clc 0(1), 0
+0xd5 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: clc 0(1), 0(%r1)
+0xd5 0x00 0x00 0x00 0x10 0x00
+
+# CHECK: clc 0(1), 0(%r15)
+0xd5 0x00 0x00 0x00 0xf0 0x00
+
+# CHECK: clc 0(1), 4095
+0xd5 0x00 0x00 0x00 0x0f 0xff
+
+# CHECK: clc 0(1), 4095(%r1)
+0xd5 0x00 0x00 0x00 0x1f 0xff
+
+# CHECK: clc 0(1), 4095(%r15)
+0xd5 0x00 0x00 0x00 0xff 0xff
+
+# CHECK: clc 0(1,%r1), 0
+0xd5 0x00 0x10 0x00 0x00 0x00
+
+# CHECK: clc 0(1,%r15), 0
+0xd5 0x00 0xf0 0x00 0x00 0x00
+
+# CHECK: clc 4095(1,%r1), 0
+0xd5 0x00 0x1f 0xff 0x00 0x00
+
+# CHECK: clc 4095(1,%r15), 0
+0xd5 0x00 0xff 0xff 0x00 0x00
+
+# CHECK: clc 0(256,%r1), 0
+0xd5 0xff 0x10 0x00 0x00 0x00
+
+# CHECK: clc 0(256,%r15), 0
+0xd5 0xff 0xf0 0x00 0x00 0x00
+
# CHECK: clfhsi 0, 0
0xe5 0x5d 0x00 0x00 0x00 0x00
@@ -4444,6 +4480,42 @@
# CHECK: msy %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x51
+# CHECK: mvc 0(1), 0
+0xd2 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: mvc 0(1), 0(%r1)
+0xd2 0x00 0x00 0x00 0x10 0x00
+
+# CHECK: mvc 0(1), 0(%r15)
+0xd2 0x00 0x00 0x00 0xf0 0x00
+
+# CHECK: mvc 0(1), 4095
+0xd2 0x00 0x00 0x00 0x0f 0xff
+
+# CHECK: mvc 0(1), 4095(%r1)
+0xd2 0x00 0x00 0x00 0x1f 0xff
+
+# CHECK: mvc 0(1), 4095(%r15)
+0xd2 0x00 0x00 0x00 0xff 0xff
+
+# CHECK: mvc 0(1,%r1), 0
+0xd2 0x00 0x10 0x00 0x00 0x00
+
+# CHECK: mvc 0(1,%r15), 0
+0xd2 0x00 0xf0 0x00 0x00 0x00
+
+# CHECK: mvc 4095(1,%r1), 0
+0xd2 0x00 0x1f 0xff 0x00 0x00
+
+# CHECK: mvc 4095(1,%r15), 0
+0xd2 0x00 0xff 0xff 0x00 0x00
+
+# CHECK: mvc 0(256,%r1), 0
+0xd2 0xff 0x10 0x00 0x00 0x00
+
+# CHECK: mvc 0(256,%r15), 0
+0xd2 0xff 0xf0 0x00 0x00 0x00
+
# CHECK: mvghi 0, 0
0xe5 0x48 0x00 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Mon Aug 12 05:17:33 2013
@@ -712,6 +712,50 @@
cl %r0, -1
cl %r0, 4096
+#CHECK: error: missing length in address
+#CHECK: clc 0, 0
+#CHECK: error: missing length in address
+#CHECK: clc 0(%r1), 0(%r1)
+#CHECK: error: invalid use of length addressing
+#CHECK: clc 0(1,%r1), 0(2,%r1)
+#CHECK: error: invalid operand
+#CHECK: clc 0(0,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: clc 0(257,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: clc -1(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: clc 4096(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: clc 0(1,%r1), -1(%r1)
+#CHECK: error: invalid operand
+#CHECK: clc 0(1,%r1), 4096(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: clc 0(1,%r0), 0(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: clc 0(1,%r1), 0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: clc 0(%r1,%r2), 0(%r1)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: clc 0(1,%r2), 0(%r1,%r2)
+#CHECK: error: unknown token in expression
+#CHECK: clc 0(-), 0
+
+ clc 0, 0
+ clc 0(%r1), 0(%r1)
+ clc 0(1,%r1), 0(2,%r1)
+ clc 0(0,%r1), 0(%r1)
+ clc 0(257,%r1), 0(%r1)
+ clc -1(1,%r1), 0(%r1)
+ clc 4096(1,%r1), 0(%r1)
+ clc 0(1,%r1), -1(%r1)
+ clc 0(1,%r1), 4096(%r1)
+ clc 0(1,%r0), 0(%r1)
+ clc 0(1,%r1), 0(%r0)
+ clc 0(%r1,%r2), 0(%r1)
+ clc 0(1,%r2), 0(%r1,%r2)
+ clc 0(-), 0
+
#CHECK: error: invalid operand
#CHECK: clfhsi -1, 0
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=188162&r1=188161&r2=188162&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Mon Aug 12 05:17:33 2013
@@ -2454,6 +2454,32 @@
cl %r0, 4095(%r15,%r1)
cl %r15, 0
+#CHECK: clc 0(1), 0 # encoding: [0xd5,0x00,0x00,0x00,0x00,0x00]
+#CHECK: clc 0(1), 0(%r1) # encoding: [0xd5,0x00,0x00,0x00,0x10,0x00]
+#CHECK: clc 0(1), 0(%r15) # encoding: [0xd5,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: clc 0(1), 4095 # encoding: [0xd5,0x00,0x00,0x00,0x0f,0xff]
+#CHECK: clc 0(1), 4095(%r1) # encoding: [0xd5,0x00,0x00,0x00,0x1f,0xff]
+#CHECK: clc 0(1), 4095(%r15) # encoding: [0xd5,0x00,0x00,0x00,0xff,0xff]
+#CHECK: clc 0(1,%r1), 0 # encoding: [0xd5,0x00,0x10,0x00,0x00,0x00]
+#CHECK: clc 0(1,%r15), 0 # encoding: [0xd5,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: clc 4095(1,%r1), 0 # encoding: [0xd5,0x00,0x1f,0xff,0x00,0x00]
+#CHECK: clc 4095(1,%r15), 0 # encoding: [0xd5,0x00,0xff,0xff,0x00,0x00]
+#CHECK: clc 0(256,%r1), 0 # encoding: [0xd5,0xff,0x10,0x00,0x00,0x00]
+#CHECK: clc 0(256,%r15), 0 # encoding: [0xd5,0xff,0xf0,0x00,0x00,0x00]
+
+ clc 0(1), 0
+ clc 0(1), 0(%r1)
+ clc 0(1), 0(%r15)
+ clc 0(1), 4095
+ clc 0(1), 4095(%r1)
+ clc 0(1), 4095(%r15)
+ clc 0(1,%r1), 0
+ clc 0(1,%r15), 0
+ clc 4095(1,%r1), 0
+ clc 4095(1,%r15), 0
+ clc 0(256,%r1), 0
+ clc 0(256,%r15), 0
+
#CHECK: clfhsi 0, 0 # encoding: [0xe5,0x5d,0x00,0x00,0x00,0x00]
#CHECK: clfhsi 4095, 0 # encoding: [0xe5,0x5d,0x0f,0xff,0x00,0x00]
#CHECK: clfhsi 0, 65535 # encoding: [0xe5,0x5d,0x00,0x00,0xff,0xff]
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