[llvm] r188016 - [mips] Delete register class HWRegs64.
Akira Hatanaka
ahatanaka at mips.com
Thu Aug 8 14:37:33 PDT 2013
Author: ahatanak
Date: Thu Aug 8 16:37:32 2013
New Revision: 188016
URL: http://llvm.org/viewvc/llvm-project?rev=188016&view=rev
Log:
[mips] Delete register class HWRegs64.
No functionality change.
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=188016&r1=188015&r2=188016&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Aug 8 16:37:32 2013
@@ -97,9 +97,6 @@ class MipsAsmParser : public MCTargetAsm
parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
MipsAsmParser::OperandMatchResultTy
- parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
-
- MipsAsmParser::OperandMatchResultTy
parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
MipsAsmParser::OperandMatchResultTy
@@ -221,7 +218,6 @@ public:
Kind_GPR32,
Kind_GPR64,
Kind_HWRegs,
- Kind_HW64Regs,
Kind_FGR32Regs,
Kind_FGR64Regs,
Kind_AFGR64Regs,
@@ -388,11 +384,6 @@ public:
return Reg.Kind == Kind_HWRegs;
}
- bool isHW64RegsAsm() const {
- assert((Kind == k_Register) && "Invalid access!");
- return Reg.Kind == Kind_HW64Regs;
- }
-
bool isCCRAsm() const {
assert((Kind == k_Register) && "Invalid access!");
return Reg.Kind == Kind_CCRRegs;
@@ -1494,36 +1485,6 @@ MipsAsmParser::parseHWRegs(SmallVectorIm
Operands.push_back(op);
Parser.Lex(); // Eat the register number.
- return MatchOperand_Success;
-}
-
-MipsAsmParser::OperandMatchResultTy
-MipsAsmParser::parseHW64Regs(
- SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
-
- if (!isMips64())
- return MatchOperand_NoMatch;
- // If the first token is not '$' we have an error.
- if (Parser.getTok().isNot(AsmToken::Dollar))
- return MatchOperand_NoMatch;
- SMLoc S = Parser.getTok().getLoc();
- Parser.Lex(); // Eat $
-
- const AsmToken &Tok = Parser.getTok(); // Get the next token.
- if (Tok.isNot(AsmToken::Integer))
- return MatchOperand_NoMatch;
-
- unsigned RegNum = Tok.getIntVal();
- // At the moment only hwreg29 is supported.
- if (RegNum != 29)
- return MatchOperand_ParseFail;
-
- MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
- Parser.getTok().getLoc());
- op->setRegKind(MipsOperand::Kind_HW64Regs);
- Operands.push_back(op);
-
- Parser.Lex(); // Eat the register number.
return MatchOperand_Success;
}
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=188016&r1=188015&r2=188016&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Aug 8 16:37:32 2013
@@ -224,7 +224,7 @@ def DSHD : SubwordSwap<"dshd", GPR64Opnd
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd, mem_ea_64>, LW_FM<0x19>;
let isCodeGenOnly = 1 in
-def RDHWR64 : ReadHardware<GPR64Opnd, HW64RegsOpnd>, RDHWR_FM;
+def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
def DEXT : ExtBase<"dext", GPR64Opnd>, EXT_FM<3>;
let Pattern = []<dag> in {
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=188016&r1=188015&r2=188016&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Aug 8 16:37:32 2013
@@ -146,7 +146,6 @@ getReservedRegs(const MachineFunction &M
// Reserve hardware registers.
Reserved.set(Mips::HWR29);
- Reserved.set(Mips::HWR29_64);
// Reserve DSP control register.
Reserved.set(Mips::DSPPos);
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=188016&r1=188015&r2=188016&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Thu Aug 8 16:37:32 2013
@@ -190,7 +190,6 @@ let Namespace = "Mips" in {
// Hardware register $29
def HWR29 : MipsReg<29, "29">;
- def HWR29_64 : MipsReg<29, "29">;
// Accum registers
def AC0 : ACC<0, "ac0", [LO, HI]>;
@@ -313,7 +312,6 @@ def HIRegs64 : RegisterClass<"Mips", [i6
// Hardware registers
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
-def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable;
// Accumulator Registers
def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
@@ -392,19 +390,10 @@ def HWRegsAsmOperand : MipsAsmRegOperand
let ParserMethod = "parseHWRegs";
}
-def HW64RegsAsmOperand : MipsAsmRegOperand {
- let Name = "HW64RegsAsm";
- let ParserMethod = "parseHW64Regs";
-}
-
def HWRegsOpnd : RegisterOperand<HWRegs> {
let ParserMatchClass = HWRegsAsmOperand;
}
-def HW64RegsOpnd : RegisterOperand<HWRegs64> {
- let ParserMatchClass = HW64RegsAsmOperand;
-}
-
def AFGR64RegsOpnd : RegisterOperand<AFGR64> {
let ParserMatchClass = AFGR64AsmOperand;
}
Modified: llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=188016&r1=188015&r2=188016&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Thu Aug 8 16:37:32 2013
@@ -403,22 +403,20 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGI
case MipsISD::ThreadPointer: {
EVT PtrVT = getTargetLowering()->getPointerTy();
- unsigned RdhwrOpc, SrcReg, DestReg;
+ unsigned RdhwrOpc, DestReg;
if (PtrVT == MVT::i32) {
RdhwrOpc = Mips::RDHWR;
- SrcReg = Mips::HWR29;
DestReg = Mips::V1;
} else {
RdhwrOpc = Mips::RDHWR64;
- SrcReg = Mips::HWR29_64;
DestReg = Mips::V1_64;
}
SDNode *Rdhwr =
CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
Node->getValueType(0),
- CurDAG->getRegister(SrcReg, PtrVT));
+ CurDAG->getRegister(Mips::HWR29, MVT::i32));
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
SDValue(Rdhwr, 0));
SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
More information about the llvm-commits
mailing list